Mission: The International Workshop on Logic and Synthesis is dedicated to research in synthesis, optimization, and verification of integrated circuits. Research on logic synthesis for emerging technologies and for novel computing platforms, such as nanoscale systems and biological systems, is also strongly encouraged. The workshop accepts complete papers as well as abstracts highlighting important new problems in the early stages of development. The emphasis is on novelty and intellectual rigor. The International Workshop on Logic and Synthesis is the premier forum for research in synthesis, optimization, and verification of integrated circuits. Research on logic synthesis for emerging technologies and for novel computing platforms, such as nanoscale systems and biological systems, is also strongly encouraged. The workshop accepts complete papers as well as abstracts, highlighting important new problems in the early stages of development, without providing complete solutions. The emphasis is on novelty and intellectual rigor. Topics of interest include (but are not limited to): synthesis and optimization; power and timing analysis; testing, validation and verification; architectures and compilation; and design experiences. Submissions on modeling, analysis and synthesis for emerging technologies and platforms are also encouraged. Both complete papers as well as extended abstracts highlighting new problems and new topics of research are welcomed. Only original and previously unpublished material is permitted. Accepted papers are distributed only to IWLS participants. The workshop format includes paper presentations, posters, invited talks, social lunch and dinner gatherings, and recreational activities.
The technical program consists of 22 regular talks, 3 invited talks, 1 special session and 4 poster presentations. The workshop will be held in Wozniak Lounge (Room 430-8 Soda Hall) at the University of California, Berkeley, Electrical Engineering and Computer Science Department.
Invited talks:
Special Session: "Software Verification and Testing"
Rates for registration::
Rates for late registration (effective May 8, 2012):
The cost of registration includes breakfasts, lunches, dinners and coffee break service. You must go to the DAC registration page in order to register for IWLS. Please follow the instructions below to register:
The IWLS community maintains a set of benchmarks, synthesized and mapped in Verilog and OpenAccess.
IWLS 2011: June 3 - June 5, 2011, San Diego, California IWLS 2010: June 18 - June 20, 2010, Irvine, California IWLS 2009: July 31 - August 2, 2009, Berkeley, California IWLS 2008: June 4 - 6, 2008, Lake Tahoe, California IWLS 2007: May 30 - June 1, 2007, San Diego, California IWLS 2006: June 7 - 9, 2006, Vail, Colorado IWLS 2005: June 8 - 10, 2005, Lake Arrowhead, California IWLS 2004: June 2 - 4, 2004, Temecula Creek, California IWLS 2003: May 28 - 30, 2003, Laguna Beach, California IWLS 2002: June 4 - 7, 2002, New Orleans, Louisiana IWLS 2001: June 12 - 15, 2001, Lake Tahoe, California IWLS 2000: May 31 - June 2, 2000, Dana Point, California
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