#!/bin/sh

#set -x

#
# Invocation:  ./runOne iscas s27_without_reset
#

if [ "x$1" = "x" -o "x$2" = "x" ]; then
  echo "usage: run-design benchmark-name file-name" 1>&2
  exit
fi

suite="$1"
design="$2"

echo "Running design $design from suite $suite"

#
# Directories and files
#
benchmark_root="../Benchmarks"
input_file="$benchmark_root/$suite/rtl/${design}.v"
sdc_file="iscas.sdc"

#
# Library stuff
#
lib=GSCLib
and_cell=AND2X1
not_cell=INVX1
seq_cell=DFFX1
mylib="my_oa_design_lib-GSCLib"

#
# Create library if neccessary
#
if [ ! -d $lib ]; then
  echo "...generating library $lib"
  verilog2oaFunc -view netlist \
                 -liberty ../Benchmarks/library/GSCLib_3.0.lib \
                 -lib $lib
fi

echo "...running verilog2oaFunc"
verilog2oaFunc -view netlist \
               -lib $mylib   \
               -verilog $input_file \
               -cell ${design}_bench > ${design}.verilog2oaFunc.log 2>&1

echo "...running simpleMap"
simpleMap -library_lib $lib   \
          -and_cell $and_cell \
          -not_cell $not_cell \
          -seq_cell $seq_cell \
          -design_lib $mylib  \
          -cell ${design}_bench      \
          -clock_net blif_clk_net \
          -save > ${design}.simpleMap.log 2>&1 


echo "...running analyzeTimine -report critical"
analyzeTiming -lib $mylib \
              -cell ${design}_bench \
              -view netlist  \
              -liberty ../Benchmarks/library/GSCLib_3.0.lib \
              -liberty_lib $lib \
              -liberty_view netlist \
              -report critical  \
              -sdc "$sdc_file" > ${design}.analyzeTiming.critical.log 2>&1

echo "...running analyzeTiming -report timing"
analyzeTiming -lib $mylib \
              -cell ${design}_bench \
              -view netlist  \
              -liberty ../Benchmarks/library/GSCLib_3.0.lib \
              -liberty_lib $lib \
              -liberty_view netlist \
              -report timing \
              -sdc "$sdc_file" > ${design}.analyzeTiming.timing.log 2>&1

echo "...running oa2verilog"
oa2verilog -lib $mylib \
           -cell ${design}_bench \
           -view netlist  \
           -verilog ${design}-simpleMap.v > ${design}.oa2verilog.log 2>&1

exit 0
