IEEE International Workshop on Logic Synthesis

IWLS 2000

Laguna Cliffs Marriott at Dana Point

5135 Park Lantern
Dana Point, CA 92629

May 31 - June 2 (right before DAC)

Web site:

sponsored by IEEE Computer Society
in cooperation with ACM SIGDA

IWLS general information

Logic Synthesis has traditionally focused on optimization techniques for combinational and sequential circuits through the manipulation of Boolean equations and state machines. IWLS 2000, the 9th workshop in this series, seeks papers both on these topics and on new directions in synthesis-based design methodology. Topics of interest include (but are not limited to):

Area, timing, power optimization Logic synthesis systems CMOS, ECL, GaAs optimization
Designer experiences with synthesis Interface specification and synthesis Digital noise and EMI
Two-Level logic optimization Interaction with physical design Multi-Level logic optimization
Incremental synthesis FSM optimization and encoding Asynchronous logic synthesis
Sequential circuit optimization Pass Transistor Logic Reachability and coverage analysis
Retiming and resynthesis Optimization at the RTL level Technology mapping
Timing verification FPGA and PLD synthesis Testing and synthesis for test
Interaction with module generators Reconfigurable computing SAT Algorithms and applications

The main goal of IWLS is to foster presentation of new ideas and work in early stages of development. For this reason, the program is very open, with high acceptance rate, heavy use of posters and short 15 min. talks for presentation, and large amounts of time in the schedule for discussions around posters. Focus group discussions are also used to encourage exchange of ideas among all the participants on ``hot'', new and controversial topics.

The accepted papers will be printed in the workshop notes which are distributed to IWLS attendants only.

Authors may submit extended abstracts for their proposed presentation. These must be no less than 1000 words and no greater than 2500 words (5 pages). These abstracts are not intended to be complete papers, but rather should contain the idea of the proposed presentation. We encourage submissions in the early stages of research which may highlight important new problems without necessarily providing complete solutions. The abstracts should be submitted through the electronic submission form.

Important Dates

Submission deadline: extended to: March 12, 2000
Notice of acceptance: April 9, 2000
Final version due: April 30, 2000

Submission of papers

Please use the electronic submission form.

IWLS information web site:

Organizing Committee

General Chair: Leon Stok (IBM)
Vice Chair: Luciano Lavagno (Universita' di Udine)
Program Chair: Michel Berkelaar (TU-Eindhoven)
Publicity Chair: Saho Hassoun (Tufts University)
Panels: Narendra Shenoy (Synopsys)
Focus Groups Organizer: Christoph Meinel (University of Trier)

Technical Program Committee

Pranav Ashar (NEC) Luca Benini (Universita' di Bologna) Michel Berkelaar (TU-Eindhoven)
Robert K. Brayton (U.C. Berkeley) Jordi Cortadella (U. Politecnica de Catalunya) Masahiro Fujita (Fujitsu Labs of America)
Soha Hassoun (Tufts University) Wolfgang Kunz (University of Frankfurt) Luciano Lavagno (Universita' di Udine)
Diana Marculescu (University of Maryland) Yusuke Matsunaga (Fujitsu Labs of Japan) Christoph Meinel (University of Trier)
Shin-Ichi Minato (NTT) Rajeev Murgai (Fujitsu Labs of America) Jose Monteiro (Univ. Tecnica de Lisboa)
Steven Nowick (Columbia University) Massoud Pedram (Univ. Southern California) Tsutomu Sasao (Kyushu Inst. of Technology)
Hamid Savoj (Magma Design Automation) Ellen Sentovich (Cadence Berkeley Labs) Narendra Shenoy (Synopsys)
Fabio Somenzi (University of Colorado) Leon Stok (IBM Watson Res.Center)