The workshop format includes short talks, posters, a panel discussion, and a social evening gathering. To further simulate interaction among participants, there will be exercises in "collaborative problem solving". Attendees will be divided into groups, each tackling a challenging problem submitted through the web and selected by the focus group chair. The EDA community is encouraged to submit possible logic and synthesis problems through http://www.iwls.org/problems/. Examples of problems will be available at the web site in early January.
Topics of interest include but are not limited to:
Architecture & Compiling Synthesis & Optimization Power & Timing Analysis Validation & Verification Design experiences
for transistor, logic, RTL, behavioral HDL, architecture, and hardware/software systems. The topics of interest span both syncronous and asynchronous domains in all technologies including: CMOS, ECL, GaAS, ECL, and Adiabatic.
|March 12, 2001|
Notice of acceptance
|April 16, 2001|
Final version due
|May 7, 2001|
Authors may submit extended abstracts for their proposed presentation. These must be no less than 1000 words and no greater than 2500 words (5 pages). These abstracts are not intended to be complete papers, but rather should contain the idea of the proposed presentation. We encourage submissions in the early stages of research which may highlight important new problems without necessarily providing complete solutions. Only electronic submissions will be accepted. See http://www.iwls.org for submission details. For questions, contact firstname.lastname@example.org.
Travel grants may be obtained by applying to ACM/SIGDA's travel grant program at http://www.sigda.acm.org/Programs/TravelGrant/
General Chair: T. Kam (Intel)
Program Chair: S. Hassoun (Tufts)
Panel Chair: D. Marculescu (CMU)
Focus Group Chair: S. Nowick (Columbia)
Benchmark Chairs: A. Kuehlmann (Cadence) and A. Reis (UFRGS, Brazil)
Program Committee:P. Ashar (NEC)