IWLS'01 Final Program

Wednesday    |  Thursday     |  Friday


Tuesday, June 12

18.00 Cocktails and Dinner

Wednesday, June 13

7.30 - 8.30 Breakfast

8.30 - 9.45 Session 1: Retiming

1.1L Characterization of Feasible Retimings
Philip Chong, Robert K. Brayton
1.2L Retiming on Flexible Circuit Structures
Jason Baumgartner, Andreas Kuehlmann
1.3L Accurate Timing Model Based Retiming and its Integration into Placement
Ingmar Neumann, Wolfgang Kunz
9.45 - 10.45  Session 2: Posters (break)
2.1PApproaches for Scheduling of Adiabatic Logic
Laszlo Varga, Ferenc Kovacs, Gabor Hosszu
2.2P An ADD-Based Symbolic Analysis of Leakage Current in CMOS Circuits
Hui-Yuan Song, R. Iris Bahar, and Joel Grodstein
2.3P A Transaction-Based Unified Simulation/Emulation Architecture for Functional Verification
Murali Kudlugi, Soha Hassoun, Charles Selvidge, Duaine Pryor
2.4P Bi-Decomposition of Multi-Valued Relations
Alan Mishchenko, Bernd Steinbach, Marek Perkowski
2.5P Wordlength-Compatible Data-Path Synthesis of Numerical Computation-Intensive Algorithms
Suhrid A. Wadekar, Alice C. Parker
2.6P Microprocessor Design Verification Using Structural Transformations
Sae Hwan Kim, John P. Hayes


10.45 - 11.50 Session 3: Mapping & Decomposition

3.1L Layout-driven Timing Optimization by Generalized DeMorgan Transform
Supratik Chakraborty, Rajeev Murgai
3.2L Efficient Canonical Form for Boolean Matching of Complex Functions in Large Libraries
Jovanka Ciric, Carl Sechen
3.3S Unate Decomposition of Boolean Functions
James Jacob, Alan Mishchenko
11.50 - 13.00 Lunch

13.00 - 14.30 Problem Solving

14.30 - 15.10 Session 4: Design Experiences

4.1L Arithmetic Logic Circuits using Self-Timed Bit-Level Dataflow and Early Evaluation
Robert B. Reese, Mitch A. Thornton, Cherrice Traver
4.2S Pass Transistor Threshold Gates. Application to WOS Filters
M. J. Avedillo, J. M. Quintana and R. Jimenez-Naharro


15.10 - 16:10 Session 5: Posters (break)

5.1P Advances in BDD reduction using Parallel Genetic Algorithms
Umberto Souza da Costa, Anamaria Martins Moreira, David Boris Paul Deharbe.
5.2P Regularity and Symmetry as a Base for Efficient Realization of Reversible Logic Circuits
Marek Perkowski, Pawel Kerntopf, Andrzej Buller, Malgorzata Chrzanowska-Jeske, Alan Mishchenko, Xiaoyu Song, Anas Al-Rabadi, Lech Jozwiak, Alan Coppola and Bart Massey
5.3P Delay Bound Determination for Timing Closure on CMOS Circuit
N. Azemard, M. Aline, P. Maurine and D. Auvergne
5.4P Reduction of Switching Noise in Low-Power CMOS Digital Circuits by Gate-level Optimization
Acosta, A.J., Parra. P., Juan, J., Valencia, M. and Jiménez, R.
5.5P Solution of Parallel Language Equations for Logic Synthesis
Nina Yevtushenko, Tiziano Villa, Robert Brayton, Alex Petrenko, Alberto Sangiovanni-Vincentelli
5.6P Synthesis of a Solution to the Yale Shooting Problem via Natural Logic With Implications for a General Solution to the Frame Problem
Charles Moeller


16:10 - 17:30 Session 6: On Multi-Valued Logic & Don't Cares

6.1L Compatible Observability Don't Cares Revisited
Robert K. Brayton
6.2S An implicit method for multi-valued network encoding
Jie-Hone Jiang, Yunjian Jiang, Robert K. Brayton
6.3S Minimization of Multiple-Valued Functions in Post Algebra
Elena Dubrova, Yunjian Jiang, Robert Brayton
6.4L MVSIS
M. Gao, J.-H. Jiang, Y. Jiang, Y. Li, S. Sinha, and R. Brayton


17.45 - 19.00 Panel: Synthesis for Nanotechnology/Nanoelectronics

Seth Goldstein, CMU,  and Shalom Wind, IBM TJ Watson


19.00 Dinner 



 

Thursday, June 14

7.30 - 8.30 Breakfast

8.30 - 9.45 Session 7: SPFDs

7.1L Sequential SPFDs
S. Sinha A. Kuehlmann R. K. Brayton
7.2L Theory and Algorithm for SPFD-Based Global Rewiring
Jason Cong and Wangning Long
7.3L Improved Robust SPFD Computations
S. Sinha R. K. Brayton
9.45 - 10.45 Session 8: Posters (break)
8.1 Automatic Extraction of Behavior from Structure
Priya Raghavan, Jacob A. Abraham, Daniel G. Saab
8.2 High Level Power Estimation based on a functional analysis for Embedded DSP Software
Johann Laurent, Nathalie Julien, Eric Senn, Eric Martin
8.3 Nonlinear Transformations of Decision Diagrams
Pawel Kerntopf
8.4 Exact Algorithm for Modifying Buffer Trees Using Buffer Duplication in a Delay Optimization Perspective
Ankur Srivastava and Majid Sarrafzadeh
8.5 Speedup of Delay-Insensitive Digital Systems Using NULL Cycle Reduction
S. C. Smith, R. F. DeMara, J. S. Yuan, M. Hagedorn, and D. Ferguson
8.6 High Probability High Density State Traversal
Chien-Pang Lu, Wen-Chien Liu, Yirng-An Chen


10.45 - 11:50 Session 9: Re-wiring

9.1L Integration of Logic Synthesis and Layout Processes by Generating Multiple Choices of Circuit Transformation
Hiroaki Yoshida, Motohiro Sera, Masao Kubo and Masahiro Fujita
9.2S Xwire: Efficient Single Wire Addition And Removal Beyond Redundancy
Chih-Wei (Jim) Chang and Malgorzata Marek-Sadowska
9.3L Recognizing Input Equivalence in Digital Logic
David E. Wallace
11.50 - 12.50 Lunch

12.50 - 13.50 Problem Solving

13.50 - 15.10 Session 10: Synthesis & Optimization

10.1L Concurrent Extraction of Partial Kernels with Timing Consideration
Peyman Rezvani and Massoud Pedram
10.2S Multi-Domain  Communication Scheduling For FPGA-based Logic Emulation
Murali Kudlugi, Russell Tessier
10.3L A Cascade Realization of Multiple-Output Function for Reconfigurable Hardware
Tsutomu Sasao, Munehiro Matsuura and Yukihiro Iguchi
10.4S A Case Study in IP Functional Customization: The UART 16550
Jiong Xie, Soha Hassoun
15.10- 16:10 Session 11: Posters (break)
11.1 Logic-Timing Simulation using the Degradation Delay Model
Juan-Chico, J., Bellido, M.J., Ruiz-de-Clavijo, P., Jimenez, C.J., Baena, C. and Valencia, M.
11.2 Symbolic Algebraic Multi-Terminal Binary Decision Diagrams with Applications to RTL Verification
Priyank Kalla, Zhihong Zeng, and Maciej J. Ciesielski
11.3 Efficient and Effective Redundacy Removal for Million-Gate Circuits
Michel Berkelaar Koen van Eijk
11.4 Multi-Valued Multi-Level Network Decomposition
Minxi Gao and Robert Brayton
11.5 A Redesign Method Based on Evaluating Quantified Boolean Formulae
Masao Kubo, Masahiro Fujita
11.6 Standard Cell Partition Size Variance and its Effect on Physical Design
Theodore W. Manikas and Gerald R. Kane
16.10 - 17:30 Session 12: Verification and Testing
12.1L Verification of Integer Multipliers on the Arithmetic Bit Level
Dominik Stoffel and Wolfgang Kunz
12.2L ART: A Functional Test Program Generation Tool
Farzan Fallah Koichiro Takayama
12.3S MINCE: A Static Global Variable-Ordering for SAT and BDD
Fadi A. Aloul, Igor L. Markov, Karem A. Sakallah
12.4S Coverage-Directed Generation of Biased Random Inputs for Functional Validation of Sequential Circuits
S. Tasiran, F. Fallah, D.G. Chinnery, S.J. Weber, K. Keutzer


17.45 Buses to Squwa Valley for the Banquet


Friday, June 15


7.30 - 8.30 Breakfast

8.30 - 9.55 Session 13: BDDs

13.1L Backtrack Search Using ZBDDs
Fadi A. Aloul Maher N. Mneimneh, Karem A. Sakallah
13.2S BDD Decomposition for the Synthesis of High Performance PTL Circuits
Rupesh S. Shelar, Sachin S. Sapatneker
13.3S Heuristics for Mod2-OBDD Minimization
Christoph Meinel, Harald Sack
13.4S Design of a Pointerless BDD Package
Geert Janssen
13.5S Hierarchical Image Computation with Dynamic Conjunction Scheduling
Christoph Meinel, Christian Stangier


9.55 - 10.05  Break

10.05 - 11.00 Session 14: Power and Timing Analysis

14.1L A Path-based Method for Statistical Delay Calculation Dealing with Correlations Due to Reconverging Paths
Etienne Jacobs
14.2S An Impulse-train Approach to Statistical Timing Analysis
Srinath R. Naidu
14.3S ALBORZ: Address Level Bus Power Optimization
Yazdan Aghaghiri, Farzan Fallah, Massoud Pedram


11.00 - 12.30 The Solved and Not Solved Problems and Discussion

12.30 - 2:30  Lunch and IWLS 2002 planning meeting