IWLS 2003 Program

Short presentations (S) - 16 minute presentation/4 minute Q and A
Long presentations (L) - 25 minute presentation/5 minute Q and A
Wednesday, May 28

12:00 - 1:00 : Lunch

1:30 - 2:30 : Layout-Aware Synthesis
chair: Victor Kravets
Layout Driven Synthesis of Data Path Circuits using Arithmetic Reasoning (S)
   I. Neumann, D. Stoffel, M. Berkelaar, and W. Kunz
Checkerboard: A Regular Structure and Its Synthesis (S)
   F. Mo and R. Brayton
A Fast Kernel Placement Algorithm for Placement-Aware Logic Synthesis (S)
   S. Chatterjee and R. Brayton

2:30 - 3:15 : Poster Session 1
Roth-Karp Decomposition Combining Functional and Structural Techniques
   A. Martinelli, R. Krenz, and E. Dubrova
Metric Definition for Circuit Speed Optimization
   X. Michel, A. Verle, P. Maurine, N. Azmard, and D. Auvergne
Synthesis of a Single-Dual-Single Wrapper for a Generalized Synchronous Variable Computation Time Arithmetic Unit
   E. Kim, H. Saito, J. Lee, D. Lee, H. Nakamura, and T. Nanya
Recursive Multi-level Circuit Clustering for Minimum Delay
   M. Dehkordi and S. Brown
Power-Aware Issue Queue Design for Speculative Instructions
   T. Moreshet and I. Bahar
Depth-Bounded Communication Complexity for Distributed Computation
   R. Jiang and R. Brayton
Evaluating Circuit Reliability Under Probabilistic Gate-Level Fault Models
   K. Patel, I. Makov, and J. Hayes
BDD-Based Boolean Satisfiability using Search Space Pruning
   S. Gopalakrishnan, V. Durairaj, and P. Kalla
Debug Methodology for Arithmetic Circuits based on Architecture Library Mapping
   M. Kubo, T, Matsumoto, and M. Fujita
Function-driven Linearly Independent Expansions of Boolean Functions and Their Application to Synthesis of Reversible Circuits
   P. Kerntopf and M. A. Perkowski
An Integrated Framework for Efficient Verification and Validation
   N. Shekhar and P. Kalla
Bit-Level Systolic Array-based Genetic Accelerator
   G.-Y. Song and J.-J. Lee

3:15 - 4:55 : Advances in Logic Synthesis
chair: Hamid Savoj
Cyclic Combinational Circuits: Analysis for Synthesis (L)
   M. Riedel and J. Bruck
Optimal Parallel-Prefix Adders using a Dynamic Programming Algorithm (S)
   J. Liu, S. Zhou, H. Zhu, K.-T. Tseng, and C. K. Cheng
Fast Multi-level Logic Optimization using Local Transformations (S)
   P. Farm and E. Dubrova
Structural Detection of Symmetries in Boolean Functions (L)
   G. Wang, A. Kuehlmann, and A. Sangiovanni-Vincentelli

4:55 - 6:00 : Focus Group Discussion

Thursday, May 29

8:30 - 9:50 : Sequential Optimization and Analysis
chair: Leon Stok
REVERSE: Efficient Sequential Verification for Retiming (S)
   M. Mneimneh and K. Sakallah
A Safe and Complete Gate-Level Register Retiming Algorithm (S)
   B. van Antwerpen, M. Hutton, G. Baeckler, and R. Yuan
Compositionally Progressive Solutions of Synchronous Language Equations (S)
   N. Yevtushenko, T. Villa, R. Brayton, A. Petrenko, and A. Sangiovanni-Vincentelli
Applying Implication-based Multi-Cycle Path Analysis to Industrial Designs (S)
   H. Higuchi

9:55 - 10:40 : Poster Session 2
Memory Efficient and Fast Boolean Matching for Large Functions Using Rectangle Representation
   M. Hutter and M. Scheppler
Folded Logic Decomposition
   D. Wu and J. Zhu
Modified Reconstructability Analysis to Implement a Novel Multi-Level Boolean Circuit Decomposition
   A. Al-Rabadi
On the Use of Autocorrelation Coefficients in the Identification of Three-Level Decompositions
   J. Rice and J. Muzio
High-Level Synthesis of Asynchronous Systems using Transformational Approaches
   D. Yoo and D. Lee
Non-Crossing Ordered BDD for Physical Synthesis of Regular Circuit Structure
   A. Cao and C. Koh
Minimization of Average Path Length in BDDs by Variable Reordering
   S. Nagayama, A. Mishchenko, T. Sasao, and J. Butler
Mapping Logic for Multiplexer-Based FPGAs
   E. S. Vadlamani, M. B. Srinivas, R. Dasari, and S. K. Kotikalapudi
Multi-Valued Optimization on Post Logic Networks
   Y. Li and R. Brayton
Asymptotically Optimal Regular Synthesis of Quantum Networks
   D. Maslov and G. Dueck
A Comparison of Generators for Testing Sequential Circuits Using BIST
   J. Zhong and J. Muzio

10:40 - 12:00 : Verification
chair: Mukul Prasad
Efficient Symbolic Model Checking using Partitioned-OBDDs (S)
   S. Iyer, C. Stangier, D. Sahoo, A. Narayan, and J. Jain
Equivalence Checking of Dissimilar Circuits (S)
   E. Goldberg and Y. Novikov
Equivalence Checking of C-based Hardware Descriptions by Using Symbolic Simulation and Program Slicer (S)
   T. Matsumoto, H. Saito, and M. Fujita
Retargetable Code Generation Based on Finite State Machine and Boolean Satisfiability (S)
   K. Seto, M, Fujita, and K. Asada

12:00 - 1:00 : Lunch

1:00 - 2:30 : Focus Group Discussions

2:30 - 4:10 : SAT, Multi-valued Analysis and Non-determinism
chair: Karem Sakallah
CAMA: A Multi-Valued Satisfiability Solver (L)
   C. Liu, A. Kuehlmann, and M. Moskewicz
Learning Schemes in 0-1 ILP (S)
   D. Chai and A. Kuehlmann
Exploring Multi-Valued Minimization Using Binary Methods (S)
   A. Mishchenko, R. Brayton, and T. Sasao
A Theory of Non-Deterministic Networks (L)
   R. Brayton and A. Mishchenko

4:15 - 5:00 : Poster Session 3: For first 15 presentations (before Thursday noon)

5:00 - 6:00 : Panel: Faults and Uncertainty: Do We Need a Totally New Approach to Properly Address These Problems?
chair: Iris Bahar
Radu Marculescu, CMU
Sani Nassif, IBM
Eric Rotenberg, North Carolina State University
Lou Scheffer, Cadence

7:00 - 10:00 : Banquet Dinner at French 75 Bistro and Champagne Bar
Please come and enjoy live piano jazz entertainment in the company of your fellow IWLS 2003 attendees.

Friday, May 30

8:30 - 9:50 : Asynchronous Synthesis
chair: Robert Brayton
A Concurrent Model for De-Synchronization (L)
   J. Cortadella, A. Kondratyev, L. Lavagno, and C. Sotiriou
Early Output Logic using Anti-Tokens (S)
   C. Brej and J. Garside
Verification of Timed Circuits with Symbolic Delays (L)
   R. Clariso and J. Cortadella

9:55 - 10:40 : Poster Session 4: For second 15 presentations (after Thursday noon)

10:40 - 12:00 : Frontiers in Synthesis
chair: Alan Mishchenko
Introduction to Reversible Logic (Invited Talk) (S)
   I. L. Markov
Templates for Toffoli Network Synthesis (S)
   D. Maslov, G. Dueck, and D. M. Miller
Scalable Simplification of Reversible Logic Circuits (S)
   V. Shende, A. Prasad, K. Patel, I. L. Markov, and J. Hayes
A Probabilistic-based Design Methodology for Nano-scale Computer Architecture (S)
   J. Chen, R. Mundy, and I. Bahar

12:00 - 1:00 : Lunch

1:30 - 3:15 : Focus Group Presentations
chair: Etienne Jacobs
Looking Back at the IWLS 1997 Focus Groups
   L. Stok

3:15 - 3:35 : Benchmark Activity Presentation - P. Kudva, I. L. Markov

3:35 - 4:20 : Poster Session 5: Open to all

4:20 - 5:50 : New Ideas in Synthesis
chair: Michel Berkelaar
An Information Theoretic Approach to Logic Evaluation (S)
   Y. Jiang and R. Brayton
On Sub-optimality and Scalability of Logic Synthesis Tools (S)
   I. L. Markov and J. Roy
Logic Styles for High Performance and Low Power (S)
   D. Samanta and A. Pal
Dynamic Fault-Tolerance Management in Failure-Prone and Battery-Powered Systems (L)
   P. Stanley-Marbell and D. Marculescu