IWLS 2010 Program

IWLS 2010 will be held in Room 6011 at Bren Hall at UC Irvine in Irvine, CA.
The closest visitor parking lot is the Anteater Parking Structure (APS). The parking rate is $8/day.
The campus map shows the APS structure in quadrants H9-H10 and Bren hall (building #314) in quadrant H8.

Friday June 18, 2010

Noon - 1:30pm : Lunch

1:30 - 2:30 : Session 1 - Logic Synthesis Optimizations
Session Chair: Igor Markov
Reduction of Interpolants for Logic Synthesis
John Backes and Marc Riedel
An Approach for Dynamic Selection of Synthesis Transformations based on Markov Decision Processes
Tobias Welp and Andreas Kuehlmann
It Is Better to Run Iterative Resynthesis on Parts of the Circuit
Petr Fiser and Jan Schmidt

2:50 - 4:10 : Session 2 - Reliability, Variability and Emerging Technologies
Session Chair: Steven Nowick
Application-Aware Diagnosis of Runtime Hardware Faults
Andrea Pellegrini and Valeria Bertacco
Circuit Level Dynamic Behavior Analysis through Timed Ternary Decision Diagram
Lu Wan and Deming Chen
SyReC: A Programming Language for Synthesis of Reversible Circuits
Robert Wille, Sebastian Offermann and Rolf Drechsler
Exploring Design and Synthesis for Optical Digital Logic
Christopher Condrat, Priyank Kalla and Steve Blair

4:15 - 5:45 : Poster Session
Self-Timed Realization of Combinational Logic
Balasubramanian Padmanabhan and Doug Edwards
Automatic Constraint Generation for Software-Based Post-Silicon Bug Repair
Hong-Zu Chou, Chia-Wei Chang, Kai-Hui Chang and Sy-Yen Kuo
TMR based Error Correction Method Considering Trade-off between Area and Soft-Error Tolerance
Shoji Harada, Masayoshi Yoshimura and Yusuke Matsunaga
Pulse Latch Based FSRs for Low-Overhead Hardware Implementation of Cryptographic Algorithms
Shohreh Sharif Mansouri and Elena Dubrova
Indicating Circuits with Area, Delay Tradeoffs
Michalis Christofilopoulos, Pavlos M. Mattheakis and Christos P. Sotiriou
Minimum-Perturbation Retiming for Delay Optimization
Sayak Ray, Alan Mishchenko, Robert K. Brayton, Stephen Jang and Thomas Daniel
Two-Level Logic Synthesis for Probabilistic Computation
Weikang Qian and Marc D. Riedel
Synthesis-Guided Partial Hierarchy Collapsing
Sayak Ray, Baruch Sterin, Alan Mishchenko and Robert K. Brayton

5.45 - 6.45 : Invited Talk I
Session Chair: Philip Brisk
Tuning in to your Body: Innovations in Wireless Health Care
Majid Sarrafzadeh

7.30 - 9.30 : Dinner at Il Fornaio Restaurant

Saturday June 19, 2010

8:00 - 8.45 : Breakfast

8:45 - 9:45 : Session 3 - Verification and Beyond
Session Chair: Robert Wille
A Single-Instance Incremental SAT Formulation of Proof- and Counterexample-Based Abstraction
Niklas Een, Alan Mishchenko and Nina Amla
Automating Unreachable Code Diagnosis and Debugging
Hong-Zu Chou, Kai-Hui Chang and Sy-Yen Kuo
Magic: An Industrial-Strength Logic Optimization, Technology Mapping, and Formal Verification Tool
Alan Mishchenko, Niklas Een, Robert Brayton, Stephen Jang, Maciej Ciesielski and Thomas Daniel

10.00 - 11.20 : Special Session I - Design for Reliability
Organizer and Moderator: Ilya Wagner
The Upside of the Reliability Downtrend
Todd Austin - Professor, University of Michigan
Approaches for the Design of Reliable Systems and their Associated Power Costs
Steven Burns - Senior Principal Engineer, Strategic CAD Labs, Intel Corp.
Computing with Stochastic Processors: Revisiting the Correctness Contract Between Software and Hardware
Rakesh Kumar - Assistant Professor, University of Illinois at Urbana-Champaign

11:35 - 12:35 : Session 4 - Synthesis and Design Flow
Session Chair: Dirk Stroobandt
A Delay-Insensitive Bus-Invert Encoding Scheme
Melinda Agyekum and Steven Nowick
SPIRE: A Retiming-based Global Physical-Synthesis Transformation System
David Papa, Smita Krishnaswamy and Igor Markov
Generating Efficient Libraries for Use in FPGA Resynthesis Algorithms
Andrew Kennings, Alan Mishchenko, Kristofer Vorwerk, Val Pevzner and Arun Kundu

12:35 - 2:00 : Lunch

2.00 - 3.20: Special Session II - Structured ASICs
Organizer and Moderator: Philip Brisk
Structured ASIC Wars: Via-programmed or Metal-programmed?
Guy Lemieux - Associate Professor, University of British Columbia
Trade-offs and Opportunities in Synthesis for Via-Programmed Devices
Herman Schmit - eASIC
Structured ASIC's at 20nm and below
Veerbhan Kheterpal - PDF Solutions

3.35 - 4.35 : Session 5 - Checking Equivalence
Session Chair: Kai-hui Chang
Combinational Techniques for Sequential Equivalence Checking
Hamid Savoj, David Berthelot, Alan Mishchenko and Robert Brayton
EQUIPE: Parallel Equivalence Checking with GPU's
Debapriya Chatterjee and Valeria Bertacco
Computing State Matching in Sequential Circuits in Application to Temporal Parallel Simulation
Dusung Kim, Daniel Gomez-Prado, Seiyang Yang, and Maciej Ciesielski

4.50 - 5.50 : Invited Talk II
Sesssion Chair: Philip Brisk
Logic on a Biological Substrate - Reverse Engineering the Brain
Lou Scheffer

7.00 - 10.30 : Banquet Dinner Cruise
by Hornblower Cruises, Newport Beach - Boarding: 7:00 - Departure: 7.30

Sunday June 20, 2010

8:45 - 9:15 : Breakfast

9:15 - 10:15 : Session 6 - Tackling Design Challenges
Session Chair: Marc Riedel
Practical Completion Detection for 2-of-N Delay-Insensitive Codes
Marco Cannizzaro, Weiwei Jiang and Steven Nowick
An NLFSR Re-Synthesis Algorithm for Delay Optimization
Jean-Michel Chabloz, Shohreh Sharif and Elena Dubrova
Improved Synthesis of Compressor Trees on FPGAs by a Hybrid and Systematic Design Approach
Hadi Parandeh-Afshar, Arkosnato Neogy, Philip Brisk and Paolo Ienne

10.30 - 11:30 : Session 7 - Boolean Functions and Cubes
Session Chair: Alan Mishchenko
A Realization of Index Generation Functions Using Modules of Uniform Sizes
Tsutomu Sasao
Non-disjunctive Decomposition of Logic Functions by Way of Resource Sharing
Maurizio Damiani
Synthesizing Cubes to Satisfy a Given Intersection Pattern
Weikang Qian and Marc Riedel

11.45 - 1.15 : Lunch