Note: Accepted and invited papers are distributed only to IWLS participants and are not published in printed proceedings registered with IEEE or ACM.

Friday June 7, 2013

8:00am - 8:45am Breakfast and Conference Opening

8:45am - 9:45am : Keynote I Session Chair: Ilya Wagner

Cross-Layer Resilient Design for Extreme Scaling and Beyond David Pan University of Texas, Austin

10:00am - 11:30am : Session 1 - Formal Methods and Applications I Session Chair: Shobha Vasudevan

A Circuit Approach to LTL Model Checking Koen Claessen Chalmers University of Technology, Niklas Een and Baruch Sterin University of California, Berkeley

k-Liveness With Disjunctive Stabilization : A Communication Fabric Case Study Sayak Ray and Robert Brayton University of California, Berkeley

QF_BV Property Directed Reachability with Mixed Type Atomic Reasoning Units Tobias Welp and Andreas Kuehlmann University of California, Berkeley

11:30pm - 12:30pm : Lunch

12:30pm - 1:30pm : Special Session - Reconfigurable Computing Session Chair: Paolo Ienne

Efficient Circuit Specialization for Dynamic Reconfiguration of FPGAs Karel Bruneel Ghent University, Belgium

Innovation in Reconfigurable, Application Specific Systems Steven Wallach Convey Computer Corporation

1:45pm - 3:15pm : Session 2 - Logic Synthesis and Optimization I Session Chair: Philip Brisk

Faster Logic Manipulation for Large Designs Alan Mishchenko and Robert Brayton University of California, Berkeley

Fast Boolean Matching for Small Practical Functions Zheng Huang, Lingli Wang Fudan University, Yakov Nasikovskiy California State University, Dominguez Hills and Alan Mishchenko University of California, Berkeley

Threshold Logic Synthesis Using Functional Composition Paradigm Augusto Silva, Mayler Martins, Renato Ribas and Andre Reis Federal University of Rio Grande do Sul

3:30pm - 5:00pm : Session 3 - Test, Verification and Reliability Session Chair: Alan Mishchenko

Online and Operand-Aware Detection of Failures by Utilizing False Alarm Vectors Amir Yazdanbakhsh, David Palframan, Azadeh Davoodi, Nam Sung Kim and Mikko Lipasti University of Wisconsin, Madison

Automatic Test Pattern Generation for Delay Defects Using Timed Characteristic Functions Shin-Yann Ho, Shuo-Ren Lin, Ko-Lung Yuan, Chien-Yen Kuo, Jie-Hong Roland Jiang and Chien-Mo Li National Taiwan University

ArChIVED: High Performance Validation of Microprocessors Using Event Digests Chang-Hong Hsu, Debapriya Chatterjee University of Michigan, Ann Arbor, Ronny Morad, Raviv Gal IBM Research Lab and Valeria Bertacco University of Michigan, Ann Arbor

6:00pm : Dinner Moonshine Patio Bar & Grill, 303 Red River Street Austin, TX

Saturday June 8, 2013

8:00am - 8:45am : Breakfast

8:45am - 9:45am : Keynote II Session Chair: Dirk Stroobandt

When Logic Synthesis Met Physical Synthesis Chuck Alpert IBM Research

10:00am - 11:30am : Session 4 - Formal Methods and Applications II Session Chair: Shobha Vasudevan

A Toolbox for Counter-Example Analysis and Optimization Alan Mishchenko, Niklas Een and Robert Brayton University of California, Berkeley

Enhancing Iterative Layering with SAT Solvers Ana Petkovska, David Novo, Ajay Kumar Verma EPFL, Alan Mishchenko University of California, Berkely and Paolo Ienne EPFL

Word-Level Abstraction from Bit-Level Circuits using Groebner Bases Tim Pruss, Priyank Kalla University of Utah and Florian Enescu Georgia State University

11:30am - 12:30pm : Lunch

12:30pm - 2:00pm : Session 5 - Stochastic and Trusted Computing Session Chair: Michael Orshansky

Sequential Logic to Transform Probabilities Naman Saraf and Kia Bazargan University of Minnesota, Twin Cities

Autocorrelation Study for Finite-State Machine-based Stochastic Computing Elements Cong Ma, Peng Li and David J. Lilja University of Minnesota, Twin Cities

Designing Trusted Circuits from Finite State Machines Carson Dunbar and Gang Qu University of Maryland, College Park

2.15pm - 3.15pm : Session 6 - Logic Synthesis and Optimization II Session Chair: Ilya Wagner

A new method for factoring read-polarity-once Boolean functions Vinicius Callegaro, Mayler Martins, Renato Ribas and Andre ReisFederal University of Rio Grande do Sul

A Structural Algorithm to Minimize Switch Count in CMOS Logic Gates Vinicius Possani Federal University of Pelotas, Vinicius Callegaro, André Reis, Renato Ribas Federal University of Rio Grande do Sul, Felipe Marques and Leomar Da Rosa Junior Federal University of Pelotas

3:30pm - 4:30pm : Session 7 - Index Generation Functions Session Chair: Gang Qu

An Efficient Implementation of The Index Generation Functions Yusuke Matsunaga Kyushu University

Cyclic Row-Shift Decompositions for Incompletely Specified Index Generation Functions Tsutomu Sasao Meiji University

4.30pm - 5.00pm : Closing Remarks

Note: Accepted and invited papers are distributed only to IWLS participants and are not published in printed proceedings registered with IEEE or ACM.