IWLS 2014 Program

Friday May 30, 2014

2:00pm - 2:15pm: Workshop Opening
Dirk Stroobandt

2:15pm - 4:15pm: Session 1 - Logic Representation and Optimization
Session Chair: André Reis
Majority Logic Representation and Satisfiability
Luca Amarù, Pierre-Emmanuel Gaillardon and Giovanni De Micheli, EPFL
Constrained Interpolation for Guided Logic Synthesis
Ana Petkovska, David Novo, EPFL, Alan Mishchenko, University of California, Berkeley and Paolo Ienne, EPFL
Accelerating SAT-based Boolean Matching for Heterogeneous FPGAs using One-hot Encoding and CEGAR Technique
Yusuke Matsunaga, Kyushu University
On the Average Number of Variables to Represent Incompletely Specified Index Generation Functions
Tsutomu Sasao, Meiji University

4:30pm - 6:00pm: Session 2 - High-Level Synthesis and Arithmetic
Session Chair: Robert K. Brayton
Efficient Static Performance Analysis of Acyclic Asynchronous Pipelines
Yi-Hsiang Lai, Chi-Chuan Chuang and Jie-Hong Roland Jiang, National Taiwan University
On the Multiplierless Design of Correctly Rounded Multiple Constant Divisions
Levent Aksoy, Paulo Flores and José Monteiro, INESC-ID
Data Reuse Buffer Synthesis for Nonrectangular Domains
Wim Meeus and Dirk Stroobandt, Ghent University

6:30pm: Dinner
Galleria Park Hotel

Saturday May 31, 2014

8:15am - 9:00am: Breakfast

9:00am - 10:00am: Keynote I
Session Organizer: Shobha Vasudevan
SAT Modulo Monotonic Theories
Alan J. Hu, University of British Columbia

10:15am - 11:15am: Session 3 - Systems and Components
Session Chair: Dirk Stroobandt
High Radix On-Chip Networks at Incremental Reconfiguration Costs
Animesh Jain, Ritesh Parikh and Valeria Bertacco, University of Michigan
Variable-Length-Key Sorter on FPGA using Tries
Hiroshige Hayashizaki, Megumi Ito, Takanori Ueda and Moriyoshi Ohara, IBM Research, Tokyo

11:30am - 12:30pm: Session 4 - Testing and Fingerprinting
Session Chair: Mihir Choudhury
Pre-mapping Fault Injection in FPGA-based Parameterised Test Set Generation for ASIC Testing
Alexandra Kourfali, Karel Bruneel and Dirk Stroobandt, Ghent University
A Practical Circuit Fingerprinting Method Utilizing Observability Don’t Care Conditions
Carson Dunbar and Gang Qu, University of Maryland

12:30pm - 1:30pm: Lunch

1:30pm - 3:30pm: Session 5 - Logic Synthesis and Optimization
Session Chair: Tsutomu Sasao
A Set of Benchmarks to Bring Logic and Physical Synthesis Together
Jody Maick Matos, Renato Ribas and André Reis, Universidade Federal do Rio Grande do Sul
m-Inductive Properties of Logic Circuits
Hamid Savoj, Alan Mishchenko and Robert Brayton, University of California, Berkeley
Matching Subcircuits with Macroblocks
Daniel MacLennan, Peter Xie, Andrew Segavac, Mark Gordon and Igor Markov, Universiry of Michigan
Enumeration of Irredundant Circuit Structures
Alan Mishchenko, University of California, Berkeley

3:45pm - 5:15pm: Special Session on Hardware Security
Session Organizer: Shobha Vasudevan
Strong Physical Unclonable Functions: A Tale of Attacks and Countermeasures
Farinaz Koushanfar, Rice University
Building Secure Reliable Hardware Roots-of-Trust: Are PUFs Enough?
Ken Mai, Carnegie Mellon University

5:30pm: Social Event

Sunday June 1, 2014

8:45am - 9:30am: Breakfast

9:30am - 11:30am: Session 6 - Logic Synthesis for Emerging Technologies
Session Chair: Alan Mishchenko
Majority-based Logic Synthesis Method for Nanometric Technologies
Mayler Martins, Vinicius Callegaro, Universidade Federal do Rio Grande do Sul, Leomar Da Rosa Jr., Felipe S. Marques, Universidade Federal de Pelotas, Renato Ribas and André Reis, Universidade Federal do Rio Grande do Sul
Comparison of Recursive and Factored Forms for Memristor Based Implication Logic
Felipe Marranghello, Mayler Martins, Vinicius Callegaro, André Reis and Renato Ribas, Universidade Federal do Rio Grande do Sul
An ISOP-based Method for Threshold Logic Identification
Augusto Neutzling, Mayler Martins, Renato Ribas and André Reis, Universidade Federal do Rio Grande do Sul
New challenges on Independent Gate FinFET Transistor Network Generation
Vinicius Possani, Universidade Federal de Pelotas, André Reis, Renato Ribas, Universidade Federal do Rio Grande do Sul, Felipe S. Marques and Leomar Da Rosa Jr., Universidade Federal de Pelotas

11:45am - 12:45pm: Keynote II
Session Organizer: Shobha Vasudevan
Visual Cortex on Silicon
Vijaykrishnan Narayanan, Penn State

12:45pm - 1:00pm: Closing Remarks
Dirk Stroobandt