Co-located with the
Design Automation Conference

26th International Workshop
on Logic & Synthesis

June 17 – 18, 2017

Thompson Conference Center — Austin, TX

Austin Area

Our sponsors


The International Workshop on Logic and Synthesis is the premier forum for research in synthesis, optimization, and verification of integrated circuits and systems. Research on logic synthesis for emerging technologies and for novel computing platforms, such as nanoscale systems and biological systems, is also strongly encouraged. The workshop encourages early dissemination of ideas and results. The workshop accepts complete papers highlighting important new problems in the early stages of development, without providing complete solutions. The emphasis is on novelty and intellectual rigor.

Call for Papers

Call for Papers in PDF

Topics of interest include, but are not limited to: hardware synthesis and optimization; software synthesis; hardware/software co-synthesis; power and timing analysis; testing, validation and verification; synthesis for reconfigurable architectures; hardware compilation for domain-specific languages; design experiences. Submissions on modeling, analysis and synthesis for emerging technologies and platforms are particularly encouraged.

The workshop format includes paper presentations, posters, invited talks, social lunch and dinner gatherings, and recreational activities. Accepted papers are distributed exclusively to IWLS participants.

Important Dates

It is mandatory to register a paper by submitting an abstract before the deadline below.

Paper abstract submission: March 5, 2017
Full paper submission: March 12, 2017 @ 11.59pm Anywhere on Earth
Notification of acceptance: April 16, 2017
Final version due: May 14, 2017

The submission deadline is final. There will be no extension.

Submission instructions

Only complete papers with original and previously unpublished material are permitted. Submissions must be no longer than 8 pages, double column, 10-point font. Accepted papers are distributed only to IWLS participants.

EasyChair IWLS 2017 submission page

IWLS 2017 Programming Contest: "Y Logic Synthesis"

In 2017, the IWLS organizing committee set up a programming contest. To participate, please follow these steps:

  1. Read the contest description.

  2. Write an algorithm that translates benchmarks in either Verilog, Aiger, or Blif format into YIG files. Some benchmarks for training are available in the examples directory.

  3. You need to submit your binary or source code until April 26, 2017. We will then generate the contest results based on benchmarks different from the training ones but of similar size. We set a timeout of 10 minutes to generate the YIGs. Please send the binary or source code via email to Mathias Soeken.

  4. We will submit the generated YIG files from your submissions until May 10, 2017 and announce all the results on this webpage.

  5. The submissions are rated according the number of gates in the YIGs. If for some benchmark no YIG exists or the algorithm reaches the timeout limit, we take the worst case size over all submissions and multiply it by 1.5. If for some benchmark an incorrect YIG exists, we take the worst case size over all submissions and multiply it by 2.

  6. You are encouraged to share your source code with the IWLS community, but it's not required or has any effect on the rating. If you want to share, you can either point us to an online repository that we will link to this and the IWLS webpage. If you prefer to share the source code only among the IWLS participants, we will copy your code onto the proceeding pen drives.

For more information, please refer to the contest website: https://github.com/msoeken/iwls2017-contest

Resources for Students
Provided by the Technical Committee on VLSI (TCVLSI) from IEEE Computer Society

Best Student Paper Award: IWLS 2017 will be giving a Best Student Paper Award to a work of outstanding quality presented at the Workshop whose first author is a student. The award consists of US$ 150 and a certificate.
Student Travel Grants: IWLS 2017 will be giving two travel grants of US$ 250 for students.

To apply for a Student Travel Grant, complete the application form through the link:

Please, contact Robert Wille (robert dot wille at jku dot at) and Rolf Drechsler (drechsle at informatik dot uni-bremen dot de) if you have any question regarding student travel grants.

Organizing Committee

General Chair Jie-Hong Roland Jiang National Taiwan University, Taiwan
Program Committee Co-Chair Rolf Drechsler University of Bremen/DFKI GmbH, Germany
Program Committee Co-Chair Robert Wille Johannes Kepler University Linz, Austria
Special Sessions Chair Pierre-Emmanuel Gaillardon University of Utah, USA
Contest Chair Mathias Soeken EPFL, Switzerland
Finance Chair Andre Reis UFRGS, Brazil
Local Arrangement Chair Mihir Choudhury IBM, USA
Publicity Chair Jody Maick Matos UFRGS, Brazil

Steering Committee

Dirk Stroobandt Ghent University, Belgium
Andre Reis UFRGS, Brazil
Rolf Drechsler University of Bremen/DFKI GmbH, Germany
Ilya Wagner Intel, US
Valeria Bertacco University of Michigan, US
Alan Mishchenko University of California Berkeley, US

Technical Program Committee (Tentative)

L. Amaru Synopsys, US V. Bertacco University of Michigan, US
P. Brisk University of California Riverside, US K.-H. Chang Avery Design Systems, US
R. Drechsler University of Bremen/DFKI, Germany E. Dubrova KTH, Sweden
S. A. Edwards Columbia University, US P. Ienne EPFL, Switzerland
N. Jayakumar Juniper Networks, US H.-R. Jiang National Chiao Tung University, ROC
J.-H. Jiang National Taiwan University, ROC T. Kam Intel, US
V. Kravets IBM T. J. Watson, US S. Krishnaswamy Columbia University, US
M. Martins Carnegie Mellon University, US A. Mishchenko U. of California Berkeley, US
S. Nowick Columbia University, US H. Parandeh Afshar Qualcomm, US
A. Pellegrini University of Michigan, US M. Purnaprajna Amrita University, India
W. Qian Shanghai Jiao Tong University, PRC A. Reis UFRGS, Brazil
R. Ribas UFRGS, Brazil L. Rosa Jr. UFPel, Brazil
K. Rupnow NTU and ADSC, Singapore M. Soeken EPFL, Switzerland
D. Stroobandt Ghent University, Belgium C. Sze IBM Research, US
T. Villa Università di Verona, Italy I. Wagner Intel, US
C.-Y. Wang National Tsing Hua University, ROC T. Welp Yale University, US
R. Wille Johannes Kepler University Linz, Austria


The IWLS community maintains a set of benchmarks, synthesized and mapped in Verilog and OpenAccess.

Links to Past Workshops

IWLS 2016: June 10 - June 11, 2016, Austin, Texas

IWLS 2015: June 12 - June 13, 2015, Mountain View, California

IWLS 2014: May 30 - June 1, 2014, San Francisco, California

IWLS 2013: June 7 - June 8, 2013, Austin, Texas

IWLS 2012: June 1 - June 3, 2012, Berkeley, California

IWLS 2011: June 3 - June 5, 2011, San Diego, California

IWLS 2010: June 18 - June 20, 2010, Irvine, California

IWLS 2009: July 31 - August 2, 2009, Berkeley, California

IWLS 2008: June 4 - 6, 2008, Lake Tahoe, California

IWLS 2007: May 30 - June 1, 2007, San Diego, California

IWLS 2006: June 7 - 9, 2006, Vail, Colorado

IWLS 2005: June 8 - 10, 2005, Lake Arrowhead, California

IWLS 2004: June 2 - 4, 2004, Temecula Creek, California

IWLS 2003: May 28 - 30, 2003, Laguna Beach, California

IWLS 2002: June 4 - 7, 2002, New Orleans, Louisiana

IWLS 2001: June 12 - 15, 2001, Lake Tahoe, California

IWLS 2000: May 31 - June 2, 2000, Dana Point, California

Mailing List

Subscribe to the IWLS mailing list. (The list is hidden and only its administrator can post to it.)

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