2018

Co-located with the
Design Automation Conference

27th International Workshop
on Logic & Synthesis

June 23 – 24, 2018

Moscone Center West — San Francisco, CA

Moscone Center

Our sponsors

     
             


IWLS 2018 Preliminary Program


Saturday June 23, 2018


8:50am - 9:00am: Workshop Opening


9:00am - 10:00am: Keynote 1
TBD


10:00am - 10:30am: Coffee Break


10:30am - 12:00am: Session 1: Synthesis Packages and Toolkits
Session Chair: TBD
Integrating an AIG Package, Simulator, and SAT Solver
Alan Mishchenko and Robert Brayton (UC Berkeley, USA)
The EPFL Logic Synthesis Libraries
Mathias Soeken, Heinz Riener, Winston Haaswijk and Giovanni De Micheli (EPFL, Switzerland)
Parallel AIG Rewriting
Vinicius Neves Possani (UFRGS, Brazili), Yi-Shan Lu (UT Austin, USA), Alan Mishchenko (UC Berkeley, USA), Keshav Pingali (UT Austin, USA), Renato Perez Ribas and Andre Inacio Reis (UFRGS, Brazil)


12:00am - 1:30pm: Lunch Break


1:30pm - 3:00pm: Session 2: Quantum, Reversible, and Reversible for Irreversible
Session Chair: TBD
Estimating Single-Target Gate T-count using Spectral Classification
Giulia Meuli, Mathias Soeken (EPFL, Switzerland), Martin Roetteler (Microsoft Research, USA), D. Michael Miller (University of Victoria, Canada), Matthew Amy (University of Waterloo, Canada), Nathan Wiebe (Microsoft Research, USA) and Giovanni De Micheli (EPFL, Switzerland)
Reversible Logic Synthesis for Incompletely Specified Functions
He-Teng Zhang and Jie-Hong Roland Jiang (National Taiwan University, Taiwan)
Exact Multi-Level Logic Benchmark Generation
Walter Lau Neto (UFRGS, Brazil), Felipe Dos Santos Marranghello (KTH, Sweden), Vinicius Neves Possani, AndrĂ© InĂ¡cio Reis and Renato Perez Ribas (UFRGS, Brazil)


3:00pm - 3:30pm: Coffee Break


3:30pm - 5:00pm: Session 3: Arithmetic and Logic
Session Chair: TBD
Logic Synthesis for Multiple-Output Linear Circuits
Tsutomu Sasao (Meiji University, Japan)
A Canonicalization Procedure of Threshold Logic Functions and Its Applications
Siang-Yun Lee, Nian-Ze Lee and Jie-Hong Roland Jiang (National Taiwan University, Taiwan)
Craig Interpolants in Finite Fields using Algebraic Geometry: Theory and Application
Utkarsh Gupta (University of Utah, USA), Irina Ilioaea (Georgia State University, USA), Priyank Kalla (University of Utah, USA), Florian Enescu (Georgia State University, USA), Vikas Rao and Arpitha Srinath (University of Utah, USA)


5:00pm - 5:30pm: IWLS 2018 Programming Contest: All the Best!
TBD


Sunday June 24, 2018


8:30am - 9:30am: Keynote 2
TBD


9:30am - 10:30am: Session 4: Decomposition and Rewriting
Session Chair: TBD
Support-Reducing Functional Decomposition for FPGA Technology Mapping
Lucas Machado and Jordi Cortadella (Universitat Politecnica de Catalunya, Spain)
Structural Rewriting in XOR-Majority Graph
Zhufei Chu (Ningbo University, China), Mathias Soeken (EPFL, Switzerland), Yinshui Xiai and Lunyao Wang (Ningbo University, China)


10:30am - 11:00am: Coffee Break


11:00am - 12:00pm: Session 5: Verification and Security
Session Chair: TBD
Coverage-Guided CTL Property Enumeration for Understanding Models of Reactive Systems
Gianluca Martino (TUHH, Germany), Heinz Riener (EPFL, Switzerland) and Goerschwin Fey (TUHH, Germany)
SWAN: Hardware Trojan Security With Ambiguous Netlists
Timothy Linscott, Valeria Bertacco, Todd Austin and Opeoluwa Matthews (University of Michigan, USA)


12:00am - 1:30pm: Lunch Break


1:30pm - 3:00pm: Special Session: Application of Boolean Circuits
Session Chair: TBD
TBD
Rene Peralta (NIST)
TBD
Cody Murray (MIT)
TBD
Massimiliano Di Ventra (UCSD)


3:00pm - 4:00pm: Coffee Break + Poster Session
Session Chair: TBD
Patch Function Input Selection Methods for Efficient Multi-Target Rectification
Yusuke Kimura, Amir Masoud Gharehbaghi and Masahiro Fujita (University of Tokyo, Japan)
Optimized Memory Architecture for Graph Processing
Abraham Addisie, Hiwot Kassa, Luwa Matthews and Valeria Bertacco (University of Michigan, USA)
Interconnect for System-in-Package Architecture
Vidushi Goyal, Luwa Mathews, Reetuparna Das and Valeria Bertacco (University of Michigan, USA)
Resolving Unknown Components in Arithmetic Circuits using Computer Algebra Methods
Vikas Rao, Utkarsh Gupta (University of Utah, USA), Irina-Georgeana Ilioaea (Georgia State University, USA), Priyank Kalla (University of Utah, USA) and Florian Enescu (Georgia State University, USA)


4:00pm - 5:30pm: Session 6: Random or Not Random
Session Chair: TBD
Bit-Flip Errors Detection using Random Partial Don't-Care Keys for a Soft-Error-Tolerant TCAM
Infall Syafalni (Logic Research Co., Japan), Tsutomu Sasao (Meiji University, Japan) and Xiaoqing Wen (Kyushu Institute of Technology, Japan)
Using Resolution Splitting to Enhance Performance of Deterministic Bit-Stream Computing
M. Hassan Najafi, Sayed Abdolrasoul Faraji, Bingzhe Li, David Lilja and Kia Bazargan (University of Minnesota, USA)
Fast-Converging, Scalable, Deterministic Bit-Stream Computing using Low-Discrepancy Sequences
M. Hassan Najafi, David Lilja and Marc Riedel (University of Minnesota, USA)


5:30pm - 5:50pm: Closing Remarks