28th International Workshop
on Logic & Synthesis

June 21 – 23, 2019

EPFL — Lausanne, Switzerland


Our sponsors


The International Workshop on Logic and Synthesis is the premier forum for research in synthesis, optimization, and verification of integrated circuits and systems. Research on logic synthesis for emerging technologies and for novel computing platforms, such as nanoscale systems and biological systems, is also strongly encouraged. The workshop encourages early dissemination of ideas and results. The workshop accepts complete papers highlighting important new problems in the early stages of development, without providing complete solutions. The emphasis is on novelty and intellectual rigor.

Topics of interest include, but are not limited to: hardware synthesis and optimization; software synthesis; hardware/software co-synthesis; power and timing analysis; testing, validation and verification; synthesis for reconfigurable architectures; hardware compilation for domain-specific languages; design experiences. Submissions on modeling, analysis, and synthesis for emerging technologies and platforms are particularly encouraged.

The workshop format includes paper presentations, posters, invited talks, social lunch and dinner gatherings, and recreational activities. Accepted papers are distributed exclusively to IWLS participants.

Technical Program

The technical program consists of 16 regular talks, 5 posters and 3 keynotes.


Logic Synthesis Challenges in EDA Industry
Patrick Vuillod, Synopsys, France

The design implementation process goes from an abstract circuit representation (C or RTL) to a physical representation. Logic synthesis techniques allows to get a good quality of results in terms of frequency, area or power consumption. We will show how they play a major role in the industrial design process how they have stayed scalable and evolved in synergy with the technology nodes advances. We will describe interesting challenges that still need to be solved.

Patrick Vuillod is part of the Synopsys R&D center in Grenoble, France. He has been working on Synopsys Implementation tools for 20 years. He has been developing optimization flows of Design Compiler, ICC2 compiler and the recently announced Fusion Compiler. He worked on a broad area of topics such as logic optimization, multi-threaded delay optimization, routing congestion estimation algorithms and physical optimization, allowing several patents and papers. Previously Patrick received a PhD from INP Grenoble with an exchange at Stanford University.

How Designing Machine Learning Hardware Can Go Wrong, and What To Do About It
Bryan Bowyer, Mentor, a Siemens Business, USA

Machine Learning (ML) inferencing hardware requires hundreds of billions of multiplications per second, hundreds of megabytes of storage for constants, and complex control logic to move data smoothly and efficiently. Most hardware teams are overwhelmed by the performance requirements combined with the number of design choices for ML hardware. The team must commit to an architecture based on limited information, and the first version of their hardware rarely works as intended: the power or area is too high; the performance is too low; or a shared resource like the bus is overloaded. If ML hardware is so complex that you cannot accurately predict critical design properties, how do you design it efficiently?

My team has worked closely with several hardware design teams as they built their first ML hardware. In order to better understand the ML hardware design process, we have also built an image classification hardware accelerator. I will share what we have learned, and how hardware design is evolving to handle complex, difficult to predict hardware designs, like machine learning.

Bryan Bowyer leads the HLS Product Design team in the Digital Design & Implementation Solutions' Division of Mentor, A Siemens Company. Bryan has created a wide range of hardware using HLS, from FFTs to AXI Interfaces in C++ and SystemC, and has worked on HLS tools for the past 20 years. Bryan received his B.S. in Computer Engineering from Oregon State University.

Algebra, Proofs and Multipliers
Armin Biere, Johannes Kepler University, Austria

Verifying arithmetic circuits such as multipliers and related circuits used to implement arithmetic units in processors or cryptographic functions remains an important problem, but in practice still requires substantial manual effort. Out-of-the-box SAT solving does not work. It was even conjectured that proving such properties requires exponential resolution proofs. In this talk we want to focus on another line of research, which is applying computer algebra to verify properties of such circuits, most prominently properties of multiplier circuits. A recent approach based on polynomial reasoning made substantial progress in this regard. We are revisiting this approach, improve on some key aspects, and also lay out some future work.

In 2004 Prof. Armin Biere joined the Johannes Kepler University in Linz, Austria, and since then chairs the Institute for Formal Models and Verification. Between 2000 and 2004 he held a position as Assistant Professor within the Department of Computer Science at ETH Zürich, Switzerland. In 1999 Biere was working for a start-up company in electronic design automation after one year as Post-Doc with Edmund Clarke at CMU, Pittsburgh, USA. In 1997 Biere received a Ph.D. in Computer Science from the University of Karlsruhe, Germany. His primary research interests are applied formal methods, more specifically formal verification of hardware and software, using model checking and related techniques with the focus on developing efficient SAT and SMT solvers. He is the author and co-author of more than 180 papers and served on the program committee of more than 130 international conferences and workshops. His most influential work is his contribution to Bounded Model Checking. Decision procedures for SAT, QBF and SMT, developed by him or under his guidance rank at the top many international competitions and were awarded 67 medals including 37 gold medals. He is a recipient of an IBM faculty award in 2012, received the TACAS most influential in the first 20 years of TACAS in 2014, the HVC'15 award on the most influential work in the last five years in formal verification, simulation, and testing, the ETAPS 2017 Test of Time Award, and the CAV Award in 2018. Besides organizing several workshops Armin Biere was co-chair of SAT'06, and FMCAD'09, was PC co-chair of HVC'12, and co-chair of CAV'14. He serves on the editorial boards of the Journal on Satisfiability, Boolean Modeling and Computation (JSAT), the Journal of Automated Reasoning (JAR), and the journal for Formal Methods in System Design (FMSD). He is an editor of the Handbook of Satisfiability and initiated and organizes the Hardware Model Checking Competition (HWMCC). From 2011-2017 he served as chair and since 2017 as vice-chair of the SAT Association and since 2012 on the steering committee of FMCAD. In 2006 Armin Biere co-founded NextOp Software Inc. which was acquired by Atrenta Inc. in 2012. Since February 2014 Prof. Armin Biere acts as chair of student affairs (Präses) for computer science, helping to organize the PhD program in computer science. During the same time until May 2015 he also acted as head of the commission of the curriculum committee (Studienkommissionsvorsitzender) for the bachelor and master program in computer science and thus was as well responsible for admission and credit transfer, for both the bachelor and master program in computer science.


    Until May 30   From May 31
ACM/IEEE members:   Students   200 CHF   300 CHF
  Others   350 CHF   500 CHF
Non ACM/IEEE members:   Students   300 CHF   400 CHF
  Others   500 CHF   650 CHF

The cost of registration includes breakfasts, lunches, dinner, social event and coffee break service.

Register for the IWLS following the instructions below:

  1. Go to https://si2.epfl.ch/PayOnline/IwslRcForm.html. This will direct you to the registration page.

  2. Complete all the contact information and enter your membership status.
Social Dinner Friday, June 21, 18:00 - 21:00

The social dinner will take place on a boat tour on Lake Geneva. The boat will depart from Lausanne-Ouchy at 18:05, so please make sure that you are on time. We will leave together from EPFL at 5pm.

Social Hike In The Vineyards

Sunday, June 23, 09:30 - 17:00: We are organizing a light social hike on Sunday, June 23, the day after the conference through the Lavaux vineyards. It is a common social event together with the participants from the Reversible Computation conference. The hike is unofficially organized and possible public transportation costs are not covered by the official registration fee. Nevertheless, please indicate that you'd like to join the hike by crossing the item in the registration form.

Each hike can be substituted by a train ride. If someone likes to join the tour later, e.g., at the restaurant or the Lac de Bret, we can find alternative train rides directly from Lausanne to these destinations. The same applies, if someone wishes to return earlier. Several volunteers will attend the hike and can assist in local transportation.

IWLS 2019 Programming Contest: "Legal AIGs"

In 2019, the IWLS organizing committee set up a programming contest. To participate, please follow these steps:

  1. Read the contest description.

  2. Write a computer program that takes as input an AIG and a constraint on the maximum number of node fanouts, that generates a legalized AIG with regard to the maximum fanout constraint as explained in the contest description.

  3. Test your solution using the contest benchmarks. These will NOT be used to evaluate your algorithms but will be similar in size/characteristics to the ones we will use to evaluate the submissions.

  4. You need to submit your binary or source code and the resulting BLIF files for the contest benchmarks until May 21, 2019.

  5. You are encouraged to share your source code with the IWLS community, but it's not required or has any effect on the rating. If you want to share, you can either point us to an online repository that we will link to this and the IWLS webpage. If you prefer to share the source code only among the IWLS participants, we will copy your code onto the proceeding pen drives.

Logic Synthesis Software School

The Logic Synthesis Software School (LSSS) is an informal meeting on software tools for logic synthesis and verification.

The goal of the meeting is to bring together researchers and tool developers in the fields of electronic design automation, logic synthesis, and verification to foster research on open science infrastructure and tools for logic synthesis and verification.

The LSSS is a joint event of IWLS and will take place on June 20 at EPFL in Switzerland.

The Logic Synthesis Software School page

Important Dates

It is mandatory to register a paper by submitting an abstract before the deadline below.

Paper abstract submission: March 17, 2019
Full paper submission: March 24, 2019 @ 11.59pm Anywhere on Earth
Notification of acceptance: May 5, 2019
Final version due: June 2, 2019

Submission Instructions

Only complete papers with original and previously unpublished material are permitted. Submissions must be no longer than 8 pages, double column, 10-point font. Accepted papers are distributed only to IWLS participants.

EasyChair IWLS 2019 submission page

Organizing Committee

General Chair Mathias Soeken EPFL, Switzerland
Program Committee Chair & Contest Chair Luca Amaru Synopsys, USA
Program Contest Co-chair Gai Liu Xilinx Inc, USA
Special Session Chair Jody Matos Silvaco, USA
Finance Chair Pierre-Emmanuel Gaillardon University of Utah, USA
Proceedings Chair Zhufei Chu Ningbo University, China
Publicity Chair Vinicius Callegaro Mentor, a Siemens Business, USA

Steering Committee

Jie-Hong Roland Jiang National Taiwan University, Taiwan
Rolf Drechsler University of Bremen/DFKI GmbH, Germany
Andre Reis UFRGS, Brazil
Dirk Stroobandt Ghent University, Belgium
Alan Mishchenko University of California Berkeley, US

Technical Program Committee