2019

28th International Workshop
on Logic & Synthesis

June 21 – 23, 2019

EPFL — Lausanne, Switzerland

EPFL

The International Workshop on Logic and Synthesis is the premier forum for research in synthesis, optimization, and verification of integrated circuits and systems. Research on logic synthesis for emerging technologies and for novel computing platforms, such as nanoscale systems and biological systems, is also strongly encouraged. The workshop encourages early dissemination of ideas and results. The workshop accepts complete papers highlighting important new problems in the early stages of development, without providing complete solutions. The emphasis is on novelty and intellectual rigor.

Topics of interest include, but are not limited to: hardware synthesis and optimization; software synthesis; hardware/software co-synthesis; power and timing analysis; testing, validation and verification; synthesis for reconfigurable architectures; hardware compilation for domain-specific languages; design experiences. Submissions on modeling, analysis and synthesis for emerging technologies and platforms are particularly encouraged.

The workshop format includes paper presentations, posters, invited talks, social lunch and dinner gatherings, and recreational activities. Accepted papers are distributed exclusively to IWLS participants.

Keynotes

Algebra, Proofs and Multipliers
Armin Biere, Johannes Kepler University, Austria

Verifying arithmetic circuits such as multipliers and related circuits used to implement arithmetic units in processors or cryptographic functions remains an important problem, but in practice still requires substantial manual effort. Out-of-the-box SAT solving does not work. It was even conjectured that proving such properties requires exponential resolution proofs. In this talk we want to focus on another line of research, which is applying computer algebra to verify properties of such circuits, most prominently properties of multiplier circuits. A recent approach based on polynomial reasoning made substantial progress in this regard. We are revisiting this approach, improve on some key aspects, and also lay out some future work.

In 2004 Prof. Armin Biere joined the Johannes Kepler University in Linz, Austria, and since then chairs the Institute for Formal Models and Verification. Between 2000 and 2004 he held a position as Assistant Professor within the Department of Computer Science at ETH Zürich, Switzerland. In 1999 Biere was working for a start-up company in electronic design automation after one year as Post-Doc with Edmund Clarke at CMU, Pittsburgh, USA. In 1997 Biere received a Ph.D. in Computer Science from the University of Karlsruhe, Germany. His primary research interests are applied formal methods, more specifically formal verification of hardware and software, using model checking and related techniques with the focus on developing efficient SAT and SMT solvers. He is the author and co-author of more than 180 papers and served on the program committee of more than 130 international conferences and workshops. His most influential work is his contribution to Bounded Model Checking. Decision procedures for SAT, QBF and SMT, developed by him or under his guidance rank at the top many international competitions and were awarded 67 medals including 37 gold medals. He is a recipient of an IBM faculty award in 2012, received the TACAS most influential in the first 20 years of TACAS in 2014, the HVC'15 award on the most influential work in the last five years in formal verification, simulation, and testing, the ETAPS 2017 Test of Time Award, and the CAV Award in 2018. Besides organizing several workshops Armin Biere was co-chair of SAT'06, and FMCAD'09, was PC co-chair of HVC'12, and co-chair of CAV'14. He serves on the editorial boards of the Journal on Satisfiability, Boolean Modeling and Computation (JSAT), the Journal of Automated Reasoning (JAR), and the journal for Formal Methods in System Design (FMSD). He is an editor of the Handbook of Satisfiability and initiated and organizes the Hardware Model Checking Competition (HWMCC). From 2011-2017 he served as chair and since 2017 as vice-chair of the SAT Association and since 2012 on the steering committee of FMCAD. In 2006 Armin Biere co-founded NextOp Software Inc. which was acquired by Atrenta Inc. in 2012. Since February 2014 Prof. Armin Biere acts as chair of student affairs (Präses) for computer science, helping to organize the PhD program in computer science. During the same time until May 2015 he also acted as head of the commission of the curriculum committee (Studienkommissionsvorsitzender) for the bachelor and master program in computer science and thus was as well responsible for admission and credit transfer, for both the bachelor and master program in computer science.

High-level synthesis
Bryan Bowyer, Mentor, a Siemens Business, USA



Traditional logic synthesis
Patrick Vuillod, Synopsys, USA





Important Dates

It is mandatory to register a paper by submitting an abstract before the deadline below.

Paper abstract submission: March 17, 2019
Full paper submission: March 24, 2019 @ 11.59pm Anywhere on Earth
Notification of acceptance: April 28, 2019
Final version due: May 26, 2019

The submission deadline is final. There will be no extension.

Submission Instructions

Only complete papers with original and previously unpublished material are permitted. Submissions must be no longer than 8 pages, double column, 10-point font. Accepted papers are distributed only to IWLS participants.

EasyChair IWLS 2019 submission page

Logic Synthesis Software School

The Logic Synthesis Software School (LSSS) is an informal meeting on software tools for logic synthesis and verification.

The goal of the meeting is to bring together researchers and tool developers in the fields of electronic design automation, logic synthesis, and verification to foster research on open science infrastructure and tools for logic synthesis and verification.

The LSSS is a joint event of IWLS and will take place on June 20 at EPFL in Switzerland.

The Logic Synthesis Software School page

Organizing Committee

General Chair Mathias Soeken EPFL, Switzerland
Program Committee Chair & Contest Chair Luca Amaru Synopsys, USA
Program Contest Co-chair Gai Liu Xilinx Inc, USA
Special Session Chair Jody Matos Silvaco, USA
Finance Chair Pierre-Emmanuel Gaillardon University of Utah, USA
Proceedings Chair Zhufei Chu Ningbo University, China
Publicity Chair Vinicius Callegaro Mentor, a Siemens Business, USA

Steering Committee

Jie-Hong Roland Jiang National Taiwan University, Taiwan
Rolf Drechsler University of Bremen/DFKI GmbH, Germany
Andre Reis UFRGS, Brazil
Dirk Stroobandt Ghent University, Belgium
Alan Mishchenko University of California Berkeley, US

Technical Program Committee

L. Amaru Synopsys, USA M. Bubna Synopsys, USA
V. Callegaro Mentor, a Siemens Business, USA K.-H. Chang Avery Design Systems, USA
M. Choudhury IBM T. J. Watson, USA S. Das Xilinx Inc., USA
R. Drechsler University of Bremen, Germany E. Dubrova KTH, Sweden
S. A. Edwards Columbia University, USA P. Fišer CTU, Czech Republic
M. Fujita University of Tokyo, Japan P.-E. Gaillardon University of Utah, USA
B. Ghavami Shahid Bahonar U. of Kerman, Iran P. Ienne EPFL, Switzerland
I.H.-R. Jiang National Taiwan University, Taiwan J.-H.R. Jiang National Taiwan University, Taiwan
V. Kravets IBM T. J. Watson, USA G. Liu Xilinx Inc, USA
F. Marranghello Synopsys, USA M. Martins Mentor, a Siemens Business, USA
J. Matos Silvaco, USA A. Mishchenko UC Berkeley, USA
A. Neutzling Cadence, UK M. Purnaprajna Amrita University, India
W. Qian Shanghai Jiao Tong U., China A. Reis UFRGS, Brazil
T. Sasao Meiji University, Japan M. Soeken EPFL, Switzerland
D. Stroobandt Ghent University, Belgium T. Villa Universita di Verona, Italy
R. Wille Johannes Kepler U., Austria C. Yu EPFL, Switzerland
Z. Zhang Cornell University, USA

Benchmarks

The IWLS community maintains a set of logic synthesis benchmarks (IWLS'05 and EPFL), available in various formats.

Mailing List

Subscribe to the IWLS mailing list. (The list is hidden and only its administrator can post to it.)

Links to Past Workshops

IWLS 2018: June 23 - June 24, 2018, San Francisco, California

IWLS 2017: June 17 - June 18, 2017, Austin, Texas

IWLS 2016: June 10 - June 11, 2016, Austin, Texas

IWLS 2015: June 12 - June 13, 2015, Mountain View, California

IWLS 2014: May 30 - June 1, 2014, San Francisco, California

IWLS 2013: June 7 - June 8, 2013, Austin, Texas

IWLS 2012: June 1 - June 3, 2012, Berkeley, California

IWLS 2011: June 3 - June 5, 2011, San Diego, California

IWLS 2010: June 18 - June 20, 2010, Irvine, California

IWLS 2009: July 31 - August 2, 2009, Berkeley, California

IWLS 2008: June 4 - 6, 2008, Lake Tahoe, California

IWLS 2007: May 30 - June 1, 2007, San Diego, California

IWLS 2006: June 7 - 9, 2006, Vail, Colorado

IWLS 2005: June 8 - 10, 2005, Lake Arrowhead, California

IWLS 2004: June 2 - 4, 2004, Temecula Creek, California

IWLS 2003: May 28 - 30, 2003, Laguna Beach, California

IWLS 2002: June 4 - 7, 2002, New Orleans, Louisiana

IWLS 2001: June 12 - 15, 2001, Lake Tahoe, California

IWLS 2000: May 31 - June 2, 2000, Dana Point, California

Related Conferences

ICCAD: International Conference on Computer-Aided Design

DATE: Design, Automation and Test in Europe

ASPDAC: Asia and South Pacific Design Automation Conference

DAC: Design Automation Conference

ISPD: International Symposium on Physical Design

ISLPED: International Symposium on Low Power Electronics and Design

IWBDA: International Symposium on Bio-Design Automation