31st International Workshop
on Logic & Synthesis

July 18 – 21, 2022

Virtual Conference

IWLS 2022 Proceedings

Please find the IWLS 2022 proceedings here

IWLS 2022 Technical Program

Day 1 Monday, July 18, 8:50am - 2:10pm Tuesday, July 19, 0:50am - 6:10am Monday, July 18, 5:50pm - 11:10pm
Day 2 Tuesday, July 19, 5:00pm - 9:15pm Wednesday, July 20, 9:00am - 1:15pm Wednesday, July 20, 2:00am - 6:15am
Day 3 Thursday, July 21, 0:00am - 5:30am Thursday, July 21, 4:00pm - 9:30pm Thursday, July 21, 9:00am - 2:30pm

Monday July 18 based in Pacific Time (PT)
08:50 - 9:00am (PT) / 12:50 - 1:00am (JST) / 5:50 - 6:00pm (CEST):
Workshop Opening
Luca Amaru, Valentina Ciriani, and Eleonora Testa
9:00 - 10:00am (PT) / 1:00 - 2:00am (JST) / 6:00 - 7:00pm (CEST):
Keynote 1: Practice on Performance Autotuning in AI Compute Chip
Peipei Zhou, University of Pittsburgh, USA
Session Chair: Luca Amaru
10:00 - 10:15am (PT) / 2:00 - 2:15am (JST) / 7:00 - 7:15pm (CEST):
10:15am - 11:30am (PT) / 2:15 - 3:30am (JST) / 7:15 - 8:30pm (CEST):
Session 1: Let’s Get Started: Scheduling, Synthesis, and ECO
Session Chair: Walter Lau Neto
RESPECT: Reinforcement Learning based Edge Scheduling on Pipelined Coral Edge TPUs
Jiaqi Yin (University of Utah, USA), Yingjie Li (University of Utah, USA), Daniel Robinson (University of Utah, USA) and Cunxi Yu (University of Utah, USA)
Talk @Youtube
Synthesizing Practical Boolean Functions Using Truth Tables
Yukio Miyasaka (UC Berkeley, USA), Alan Mishchenko (UC Berkeley, USA), John Wawrzynek (UC Berkeley, USA) and Nicholas J. Fraser (Xilinx Research Labs, Ireland)
Talk @Youtube
Design Rectification via Abstraction Refinement and Relevance Classification
Victor Kravets (IBM, USA), Jie-Hong R. Jiang (National Taiwan University, Taiwan) and Gi-Joon Nam (IBM, USA)
Talk @Youtube
11:30 - 11:45am (PT) / 3:30 - 3:45am (JST) / 8:30 - 8:45pm (CEST):
11:45 - 12:30pm (PT) / 3:45 - 4:30am (JST) / 8:45 - 9:30pm (CEST):
Programming Contest: Presentation and Results
Session Chair: Alan Mishchenko (UC Berkeley, USA)
Talk @Youtube
11:45 - 12:00pm (PT) / 3:45 - 4:00am (JST) / 8:45 - 9:00pm (CEST):
Contest introduction
Alan Mishchenko
1st place
team EPFL (École polytechnique fédérale de Lausanne)
Andrea Costamagna, Siang-Yun Lee, Alessandro Tempia Calvino, Hanyu Wang, Mingfei Yu, Professor Giovanni de Micheli
Talk @Youtube
3rd place
team TUW (Technische Universität Wien)
Franz Reichl, Friedrich Slivovsky, Stefan Szeider
Talk @Youtube
2nd place
Team UCB (University of California, Berkeley)
Yukio Miyasaka
Talk @Youtube
12:30 - 12:45pm (PT) / 4:30 - 4:45am (JST) / 9:30 - 9:45pm (CEST):
12:45 - 2:10pm (PT) / 4:45 - 6:10am (JST) / 9:45 - 11:10pm (CEST):
Session 2: Latest on Logic Synthesis for Area and Delay
Session Chair: Victor Kravets
Extending Rewiring: Reshuffling Don't Cares to Unlock More Optimization
Eleonora Testa (Synopsys Inc, USA), Luca Amaru (Synopsys Inc, USA) and Patrick Vuillod (Synopsys Inc, France)
Talk @Youtube
Control Logic Restructuring for Area Optimization
Alan Mishchenko (UC Berkeley, USA), Robert Brayton (UC Berkeley, USA), Walter Lau Neto (University of Utah, USA), Pierre-Emmanuel Gaillardon (University of Utah, USA) and Luca Amaru (Synopsys Inc, USA)
Talk @Youtube
Revisiting SAT-Based Resubstitution for Incremental Mapped Optimization
Vinicius Possani (Synopsys Inc, USA), Luca Amaru (Synopsys Inc, USA) and Patrick Vuillod (Synopsys Inc, France)
Talk @Youtube
Timing Driven Synthesis for Open Source Tools (Short presentation)
Ashton Snelgrove (University of Utah, USA), Nichols Crawford Taylor (University of Utah, USA), Scott Temple (University of Utah, USA) and Pierre-Emmanuel Gaillardon (University of Utah, USA)
Talk @Youtube

Wednesday July 20 based in Japan Standard Time (JST)
5:00 - 6:00pm (PT) / 9:00 - 10:00am (JST) / 2:00 - 3:00am (CEST):
Keynote 2: Agile Spatial Hardware Specialization
Yun (Eric) Liang, Peking University, China
Session Chair: Eleonora Testa
6:00 - 6:15pm (PT) / 10:00 - 10:15am (JST) / 3:00 - 3:15am (CEST):
6:15 - 7:30pm (PT) / 10:15 - 11:30am (JST) / 3:15 - 4:30am (CEST):
Special Session: GPU-accelerated EDA
Session Chair: Cunxi Yu
Talk 1: Timing Analysis and Optimization on Heterogeneous CPU-GPU Platforms
Speaker: Yibo Lin, Peking University, China
Talk 2: GPU-Accelerated AIG Rewriting
Speaker: Shiju Lin, The Chinese University of Hong Kong (CUHK)
Talk 3: From RTL to CUDA: A GPU Acceleration Flow for RTL Simulation with Batch Stimulus
Speaker: Tsung-wei Huang, University of Utah, USA
7:30 - 7:45pm (PT) / 11:30 - 11:45am (JST) / 4:30 - 4:45am (CEST):
7:45 - 9:00pm (PT) / 11:45 - 1:00pm (JST) / 4:45 - 6:00am (CEST):
Session 3: Synthesis and Verification for Emerging Technologies
Session Chair: Zhufei Chu
A Complete Library of Optical Cross-Bar Gate Logic with Three Control Inputs
Ryosuke Matsuo (Kyoto University, Japan) and Shin-ichi Minato (Kyoto University, Japan)
Talk @Youtube
Depth-optimal Buffer and Splitter Insertion and Optimization in AQFP Circuits
Alessandro Tempia Calvino (EPFL, Switzerland) and Giovanni De Micheli (EPFL, Switzerland)
Talk @Youtube
Partial Equivalence Checking of Quantum Circuits
Tian-Fu Chen (National Taiwan University, Taiwan), Jie-Hong Roland Jiang (National Taiwan University, Taiwan) and Min-Hsiu Hsieh (National Taiwan University, Taiwan)
Talk @Youtube
9:00 - 9:15pm (PT) / 1:00 - 1:15pm (JST) / 6:00 - 6:15am (CEST):
EPFL Benchmark Results Update
Alessandro Tempia Calvino (EPFL, Switzerland)

Thursday July 21 based in Central European Summer Time
12:00 - 1:00am (PT) / 4:00 - 5:00pm (JST) / 9:00 - 10:00am (CEST):
Keynote 3: High-Level Synthesis of Dynamically Scheduled Circuits
Lana Josipović, ETH Zurich, Switzerland
Session Chair: Valentina Ciriani
1:00 - 1:15am (PT) / 5:00 - 5:15pm (JST) / 10:00 - 10:15am (CEST):
1:15 - 2:30am (PT) / 5:15 - 6:30pm (JST) / 10:15 - 11:30am (CEST):
Session 4: Logic Synthesis for Emerging Technologies and Classical SOP Forms
Session Chair: Giulia Meuli
Fanout-Bounded Logic Synthesis for Emerging Technologies - A Top-Down Approach
Dewmini Sudara Marakkalage (EPFL, Switzerland) and Giovanni De Micheli (EPFL, Switzerland)
Talk @Youtube
A Cost-generic Resubstitution Algorithm with Customizable Cost Functions
Hanyu Wang (ETH Zurich, Switzerland), Siang-Yun Lee (EPFL, Switzerland) and Giovanni De Micheli (EPFL, Switzerland)
Talk @Youtube
Two-Level Minimization for Partially Defined Logic Functions
Tsutomu Sasao (Meiji University, Japan)
Talk @Youtube
2:30 - 2:45am (PT) / 6:30 - 6:45pm (JST) / 11:30 - 11:45am (CEST):
2:45 - 4:00am (PT) / 6:45 - 8:00pm (JST) / 11:45am - 1:00pm (CEST):
Session 5: Testing and Boolean Satisfiability
Session Chair: Augusto Neutzling
An Automated Testing and Debugging Toolkit for Gate-Level Logic Synthesis Applications
Siang-Yun Lee (EPFL, Switzerland), Heinz Riener (Cadence Design Systems, Germany) and Giovanni De Micheli (EPFL, Switzerland)
Best Student Paper Award
Talk @Youtube
Quantifier Elimination in Stochastic Boolean Satisfiability
Hao-Ren Wang (National Taiwan University, Taiwan), Kuan-Hua Tu (National Taiwan University, Taiwan), Jie-Hong Roland Jiang (National Taiwan University, Taiwan) and Christoph Scholl (University of Freiburg, Germany)
Talk @Youtube
Improved Large-Scale SAT Sweeping
He-Teng Zhang (National Taiwan University, Taiwan), Jie-Hong Roland Jiang (National Taiwan University, Taiwan), Alan Mishchenko (UC Berkeley, USA) and Luca Amaru (Synopsys Inc, USA)
Talk @Youtube
4:00 - 4:15am (PT) / 8:00 - 8:15pm (JST) / 1:00 - 1:15pm (CEST):
4:15 - 5:30am (PT) / 8:15 - 9:30pm (JST) / 1:15 - 2:30pm (CEST):
Session 6: Compositional Synthesis, Transition Systems, and Verification
Session Chair: Petr Fišer
Polynomial Formal Verification of Approximate Adders
Martha Schnieber (University of Bremen, Germany), Saman Froehlich (University of Bremen, Germany) and Rolf Drechsler (University of Bremen, Germany)
Best Presentation Award
Talk @Youtube
A case study of transition system decomposition into sets of synchronizing Free-choice Petri nets
Viktor Teren (Università degli Studi di Verona, Italy), Jordi Cortadella (Universitat Politecnica de Catalunya, Spain) and Tiziano Villa (Università degli Studi di Verona, Italy)
Talk @Youtube
Language Equation Solving via Boolean Automata Manipulation
Wan-Hsuan Lin (National Taiwan University, Taiwan), Chia-Hsuan Su (National Taiwan University, Taiwan) and Jie-Hong Roland Jiang (National Taiwan University, Taiwan)
Talk @Youtube