2025

34th International Workshop
on Logic & Synthesis

June 12–13, 2025

University of Verona, Verona, Italy

ETH

Our sponsors

        

The International Workshop on Logic and Synthesis is the premier forum for research in synthesis, optimization, and verification of integrated circuits and systems. Research on logic synthesis for emerging technologies and for novel computing platforms, such as nanoscale systems and biological systems, is also strongly encouraged. The workshop encourages the early dissemination of ideas and results. The workshop accepts complete papers highlighting important new problems in the early stages of development, without providing complete solutions. The emphasis is on novelty and intellectual rigor.

Topics of interest include but are not limited to: hardware synthesis and optimization; software synthesis; hardware/software co-synthesis; power and timing analysis; testing, validation, and verification; synthesis for reconfigurable architectures; hardware compilation for domain-specific languages; and design experiences. Submissions on modeling, analysis, and synthesis for emerging technologies and platforms are particularly encouraged.

The workshop format includes paper presentations, invited talks, social lunch and dinner gatherings, and recreational activities.

Check out our call for papers.

Important Dates

Paper abstract submission: March 21, 2025 (AoE) March 28, 2025 (AoE)
Full paper submission: March 28, 2025 (AoE) April 4, 2025 (AoE)
Notification of acceptance: May 3, 2025
Final version due: May 30, 2025

Submission Instructions

Only complete papers with original and previously unpublished material are permitted. Submissions must be no longer than 8 pages (reference excluded), double column, 10-point font (we recommend using the ACM template or the IEEE template, but not necessarily). Accepted papers are distributed only to IWLS participants.

Double-blind policy: IWLS uses a double-blind reviewing system. Manuscripts must not identify authors or their affiliations; those that do will not be considered.

If you have questions about how to meet these guidelines, please contact the program chairs before the submission deadline.

EasyChair IWLS 2025 submission page

IWLS Programming Contest

The competition this year is a continuation of the IWLS competitions held in the last three years. The decision to continue the competition is based on the observation that the quality of the results has not saturated. Indeed, the competition started in 2022, and the results produced by the participants in 2023 were on average 15% better that those in 2022. Similarly, the results in 2024 were on average 8% better than those in 2023. It will be interesting to see how much progress will be achieved this year.

For details, please check out the call for submission for the programming contest below.

IWLS 2025 Programming Contest Call for Submissions

Benchmarks. The competition has two sets of benchmarks: the first set of benchmarks is identical to that used in 2022; the second set of benchmarks is composed of unmodified and unobfuscated practical circuits, many of which currently pose problems for hardware designers and EDA tool flows.

IWLS 2022 Programming Contest Benchmarks

IWLS 2025 Programming Contest Benchmarks

Submission deadline: June 5, 2025 (AoE)

Submission site: IWLS 2025 Contest Submission

Keynotes


Stronger Together: Bridging Logic Synthesis and Side-Channel Analysis
Elena Dubrova, Royal Institute of Technology (KTH), Sweden

Abstract:
Side-channel attacks exploit information leaked through non-primary channels, such as power consumption, electromagnetic emissions, or timing, to extract sensitive data from cryptographic devices. Over the past three decades, side-channel analysis has developed into a mature research field with well-established methodologies for analyzing standard cryptographic algorithms like the Advanced Encryption Standard (AES). In this talk, we will describe the benefits of applying Boolean reasoning techniques from logic synthesis area to side-channel analysis. As a case study, we present a hybrid attack on AES that combines side-channel analysis with SAT. We model AES as a SAT problem and incorporate information about the input and output values of the S-boxes, extracted using profiled deep learning-based power analysis, to solve it. Experimental results on a software implementation of AES-128 show that the SAT-assisted approach consistently recovers the full encryption key within one hour using a single power trace. In contrast, without SAT assistance, the success rate remains below 80% after 26 hours of key enumeration.

Speaker bio:
Elena Dubrova received the Diploma Engineer degree in Computer Science from Technical University of Sofia, Bulgaria, in 1993, and Ph.D. degree in Computer Science from University of Victoria, B.C., Canada, in 1998. Since 2008 she has been a professor at the School of Electrical Engineering and Computer Science at the Royal Institute of Technology, Stockholm, Sweden. She has over 100 publications and 15 granted patents. Her work has been awarded prestigious prices such as IBM faculty partnership award for outstanding contributions to IBM research and development. She is a world's top 2% scientist according to the Stanford University ranking from 2020. Her research interests include hardware security, lightweight cryptography, logic synthesis, and multiple-valued logic.

Tsetlin Machines: Towards Energy-Efficient and Explainable AI via Logic and Expediency in Learning
Alex Yakovlev, Newcastle University, UK

Abstract:
Artificial Intelligence (AI) and Machine Learning (ML) enter our lives in many forms, from high-end data processing and mining for applications such as medical diagnosis and cyber-commerce to low-end intelligent interfaces (mobile and internet of things (IoT) devices) for voice and image recognition applications. More recently, ML has been gradually entering traditional algorithmic domains such as design automation. The key challenges on this path are the issues of, firstly, high cost of conventional ML methods, such as deep learning (e.g. DNNs), in terms of energy and computational resources, and secondly, the lack of interpretability of the models. Tsetlin Machine (TM) is a recent logic-based model for reinforcement learning, which builds on the legacy of the pioneering ideas of Mikhail Tsetlin from 1960s in building expedient learning automata. TM has demonstrated competitive accuracy on many popular benchmarks while providing a natural interpretability as well as energy-efficiency, enabling this model for both inference and training at the edge. The talk will provide an overview of TM architecture and its parameter tuning as well as experiences in implementing TMs in software and hardware (FPGAs and ASICs). It will also highlight some opportunities and challenges on the way towards the use of Tsetlin’s ideas in EDA.

Speaker bio:
Alex Yakovlev, PhD (1982), DSc (2006). Since 1991 he is with Newcastle University, UK, where he is a Professor of Computer Systems Design, founded and leads the Microsystems Research Group, and co-founded the Asynchronous Systems Laboratory. He was awarded an EPSRC Dream Fellowship in 2011–2013. He has published in the areas of concurrent and asynchronous circuits and systems, Petri nets, electronic design automation, low power circuits and systems, AI and machine learning hardware based on Tsetlin automata and electromagnetic computing, with several best paper awards and nominations. He co-invented Signal Transition Graphs (STGs) and co-led developments of tools for them (Petrify, Workcraft) throughout the last 40 years. He has supervised over 70 PhD students. He is a Fellow of Royal Academy of Engineering and Fellow of IEEE. He is a co-founder of a recently created spin-out company Literal Labs (formerly Mignon Technologies), commercialising solutions for ML at the edge.

High-Level Synthesis: Transforming the Design of Heterogeneous System-on-Chips
Marcello Dusini, Gianluca Rigano, and David Vincenzoni, STMicroelectronics, Italy

Abstract:
High-Level Synthesis (HLS) offers significant advantages over traditional design methodologies for implementing complex digital systems. In our design perimeter, we primarily deal with heterogeneous System-on-Chip (SoCs). These circuits contain a variety of different embedded processors, memories, peripherals (e.g. QSPI, I2C) and multiples dedicated hardware accelerators (HWaccs), all interconnected through an on-chip bus. Hardware accelerators are fixed hardware modules that execute a specific application, such as signal processing, with great performance advantages compared to their execution on a general-purpose processor at the same energy consumption. HLS is particularly suitable for designing these processing elements in modern SoCs. Raising the level of hardware design abstraction from a register-transfer level (RTL) to a behavioral level offers several benefits. Firstly, it simplifies the design process, as writing C/C++ code does not require consideration of aspects such as time scheduling of operations or clock/reset handling. Furthermore, the untimed behavioral level accelerates the initial verification process. It can be compiled using a standard software compiler like gcc or g++, leading to very fast cycle-accurate simulations, with up to 10x time savings compared to RTL simulations. In this talk, we will explore examples of signal processing algorithms developed in C++/SystemC and MatlabÂź that have been implemented using the HLS flow. A more relevant and unique advantage of HLS is the ability to generate a number of functionally equivalent versions of a design, getting optimized flavors depending on different scenarios; thus, several design variants can be obtained by setting synthesis directives in the form of pragmas or by selecting options in the HLS tool; different combinations of these directives result in designs with the varying area, performance and power trade-offs.

Speakers bio:
Marcello Dusini is a seasoned professional with over 25 years of experience in digital design. He graduated from the University of Bologna in 1998, specializing in microelectronics and computer architectures before joining ST Microelectronics in 2000. Marcello started his career working on implementation flows for ARM architectures within a cross-border team located in both in Italy and France. During this time, he contributed to ST's first 45nm test chip. With years in the field, he moved to product design, developing deep skills in UVM and Formal methodologies. He has been writing RTL code for various peripherals for different applications. He successfully developed a complete prefetch buffer with cache features for the CortexM3 using an exclusively formal approach. Recently, he has developed applications using Python to enhance the efficiency of the design flow.

Gianluca Rigano graduated in Electronic Engineering from Politecnico di Torino in December 2016, following the electronic systems program. He began his professional experience in STMicroelectronics in 2017 as an application engineer, and after two years, transitioned to his current role as an IC designer and verification engineer for industrial, NB-IoT and smart metering applications. Over these years, Gianluca has gained experience in the best technologies and methodologies related to digital verification, such as formal verification and UVM, as well as in various design activities for functional and testing purposes. In addition to his work activities, last summer he earned a second-level Master’s degree in collaboration with Politecnico di Milano, which delved into each step of the IC design flow, from system design up to the layout stage.

David Vincenzoni is an Electronic Engineer with over 25 years of experience in the field of digital design and signal processing. After graduating with a major in Telecommunication in 1996, David began working on R&D projects focused on algorithm research for digital signal processing systolic arrays and their FPGA implementations. He then transitioned to more operational roles in digital design as a Project Leader, working on several SoCs based on ARM architecture, as well as digital IP design, and verification. In 2007, David joined STMicroelectronics as a Design Manager, where he has been responsible for the design and verification of SoCs and industrial ASIC applications. He has become an expert in formal verification, creating advanced flows and improved methodologies that were already considered state of the art. He was one of the first to introduce IP formal sign-off flow, which has since become a widely adopted industry standard. Since 2024, he is a Senior Member of the Technical Staff at ST.


Travel Information

The location of the workshop venue and nearby hotels will be available soon.

Organizing Committee

General Chair Valentina Ciriani University of Milan
Program Committee Chairs Walter Lau Neto
Weikang Qian		 Synopsys
Shanghai Jiao Tong University
Program Contest Chairs Alan Mishchenko
Alessandro Tempia Calvino 		UC Berkeley
Synopsys
Special Session Chair Tiziano Villa University of Verona
Finance Chair Lana Josipović ETH Zurich
Proceedings Chair Anna Bernasconi University of Pisa
Publicity Chairs Petr FiĆĄer
Jiahui Xu		 Czech Technical University in Prague
ETH Zurich
Local Arrangements Chairs Tiziano Villa
Davide Quaglia
Asma Taheri Monfared		 University of Verona
University of Verona
University of Bergamo

Technical Program Committee

Luca AmarĂč   Synopsys, USA
Anna Bernasconi   University of Pisa, Italy
Lei Chen   Huawei Noah’s Ark Lab, Hong Kong SAR
Zhufei Chu   Ningbo University, China
Valentina Ciriani   University of Milan, Italy
Fabrizio Ferrandi   Politecnico di Milano, Italy
Petr FiĆĄer   Czech Technical University in Prague, Czech Republic
Aman Gayasen   AMD, USA
Winston Haaswijk   Cadence Design Systems, USA
Jie-Hong Roland Jiang   National Taiwan University, Taiwan
Attila Jurecska   Siemens EDA, USA
Victor Kravets   IBM, USA
Walter Lau Neto   Synopsys, USA
Chang Meng   EPFL, Switzerland
Giulia Meuli   Synopsys, USA
Chin-ichi Minato   Kyoto University, Japan
Alan Mishchenko   University of California, Berkeley, USA
Augusto Neutzling   Real Intent, USA
Stefan Nikolić   University of Novi Sad, Serbia
Weikang Qian   Shanghai Jiao Tong University, China
Stefano Quer   Politecnico di Torino, Italy
Andre Reis   UFRGS, Brazil
Tsutomu Sasao   Meiji University, Japan
Herman Schmit   Google, USA
Eleonora Testa   Synopsys, USA
Gabriella Trucco   University of Milan, Italy
Tiziano Villa   University of Verona, Italy
Robert Wille   TU Munich & SCCH GmbH, Germany
Cunxi Yu   University of Maryland, College Park, USA
Mingfei Yu   EPFL, Switzerland

Benchmarks

The IWLS community maintains a set of logic synthesis benchmarks (IWLS'05 and EPFL), available in various formats.

Mailing List

Subscribe to the IWLS mailing list. (The list is hidden and only its administrator can post to it.)

Links to Past Workshops

IWLS 2024: June 6 - June 7, 2024, Zurich, Switzerland

IWLS 2023: June 5 - June 5, 2023, Lausanne, Switzerland

IWLS 2022: July 18 - July 22, 2022, Virtual

IWLS 2021: July 19 - July 22, 2021, Virtual

IWLS 2020: July 27 - July 30, 2020, Virtual

IWLS 2019: June 21 - June 23, 2019, Lausanne, Switzerland

IWLS 2018: June 23 - June 24, 2018, San Francisco, California

IWLS 2017: June 17 - June 18, 2017, Austin, Texas

IWLS 2016: June 10 - June 11, 2016, Austin, Texas

IWLS 2015: June 12 - June 13, 2015, Mountain View, California

IWLS 2014: May 30 - June 1, 2014, San Francisco, California

IWLS 2013: June 7 - June 8, 2013, Austin, Texas

IWLS 2012: June 1 - June 3, 2012, Berkeley, California

IWLS 2011: June 3 - June 5, 2011, San Diego, California

IWLS 2010: June 18 - June 20, 2010, Irvine, California

IWLS 2009: July 31 - August 2, 2009, Berkeley, California

IWLS 2008: June 4 - 6, 2008, Lake Tahoe, California

IWLS 2007: May 30 - June 1, 2007, San Diego, California

IWLS 2006: June 7 - 9, 2006, Vail, Colorado

IWLS 2005: June 8 - 10, 2005, Lake Arrowhead, California

IWLS 2004: June 2 - 4, 2004, Temecula Creek, California

IWLS 2003: May 28 - 30, 2003, Laguna Beach, California

IWLS 2002: June 4 - 7, 2002, New Orleans, Louisiana

IWLS 2001: June 12 - 15, 2001, Lake Tahoe, California

IWLS 2000: May 31 - June 2, 2000, Dana Point, California

Related Conferences

ICCAD: International Conference on Computer-Aided Design

DATE: Design, Automation and Test in Europe

ASPDAC: Asia and South Pacific Design Automation Conference

DAC: Design Automation Conference

ISPD: International Symposium on Physical Design

ISLPED: International Symposium on Low Power Electronics and Design

IWBDA: International Symposium on Bio-Design Automation