2024

33rd International Workshop
on Logic & Synthesis

June 6–7, 2024

ETH Zurich, Zurich, Switzerland

ETH

Our sponsors

           

The International Workshop on Logic and Synthesis is the premier forum for research in synthesis, optimization, and verification of integrated circuits and systems. Research on logic synthesis for emerging technologies and for novel computing platforms, such as nanoscale systems and biological systems, is also strongly encouraged. The workshop encourages the early dissemination of ideas and results. The workshop accepts complete papers highlighting important new problems in the early stages of development, without providing complete solutions. The emphasis is on novelty and intellectual rigor.

Topics of interest include but are not limited to: hardware synthesis and optimization; software synthesis; hardware/software co-synthesis; power and timing analysis; testing, validation, and verification; synthesis for reconfigurable architectures; hardware compilation for domain-specific languages; and design experiences. Submissions on modeling, analysis, and synthesis for emerging technologies and platforms are particularly encouraged.

The workshop format includes paper presentations, invited talks, social lunch and dinner gatherings, and recreational activities.

Check out our call for papers.

Thank You All for Participating in IWLS 2024!

ETH

IWLS 2024 Best Student Paper Award:

🏆 Information Graph-Based Resubstitution For Networks of Look-Up Tables. Andrea Costamagna (EPFL), Alessandro Tempia Calvino (EPFL), Alan Mishchenko (UC Berkeley), and Giovanni De Micheli (EPFL)

IWLS 2024 Programming Contest Winners:

đŸ„‡ 1st place: NUP (Neapolis University Pafos). Daniil Averkov, Gregory Emdin, Mikhail Goncharov, Alexander S. Kulikov, Daniil Levtsov, Georgie Levtsov, Vsevolod Vaskin, Aleksey Vorobiev

đŸ„ˆ 2nd place: ALCom Lab (National Taiwan University and MediaTek). Yu-Hao Ko, Shao-Jui Wu, Jie-Hong Roland Jiang, Wei-Chen Chien

đŸ„‰ 3rd place: USTC and Huawei (University of Science and Technology of China and Huawei). Qingyue Yang, Zhihai Wang, Lei Chen, Xing Li, Yiwen Wang, Mingxuan Yuan, Jianye Hao, Jie Wang, Bin Li, Yongdong Zhang, Feng Wu

👏 Honorable mention: Kapenga (Independent researcher). Wybren Kapenga

More details can be found on the IWLS 2024 contest website [click here]

IWLS 2024 keynote and special session slides are available—check out below and the technical program page!

IWLS 2024 gallery: [click here]

Technical Program Released!

Full Technical Program

The program consists of 6 regular paper sessions, 1 poster session, 3 keynotes, and 1 special session.

Keynotes

Can AI Design and Verify Your Design? [Slides]
Ziyad Hanna, Cadence Design Systems, Israel

Abstract: In this talk, I will explore the significant impact of artificial intelligence (AI) in addressing the mounting complexity and demands within chip design domain. With an anticipated exponential growth in annual revenue reaching the trillion-dollar mark, driven by the rapid growth in key markets in 5G, Hyperscalers, autonomous vehicles, AI, and industrial IoT. The chip design market is trending into a fourfold increase in project volume with tenfold complexity. The current design and verification methodologies are lacking in capacity to meet this surge, highlighting the shortage of qualified engineers to meet the aggressive market demand. AI technologies stand at the forefront of transforming design and verification processes, offering unparalleled efficiency and cost-effective solutions to meet the escalating market needs. In this talk, I will address the inherent challenges in the chip design industry, analyze the current landscape of automation, machine learning (ML), and cutting-edge generative AI technologies. I will also discuss a strategic direction for harnessing AI to enhance design synthesis and verification, including the automatic generation of programs supported by natural language processing (NLP) and generative AI, the creation of temporal assertions from design specifications, the integration of high-level synthesis (HLS) and formal verification, and the exploration of the latest advancements in AI technologies for full design and verification flow for achieving the aggressive demand on performance, power and area. Furthermore, the presentation emphasizes the essence for collaborative initiatives between industry and academia to drive forward transformative advancements and innovations within the chip design and verification domain with AI.

Ziyad Hanna, Ph.D., is currently a corporate VP at Cadence Design Systems (CDNS), and the general manager of Cadence Israel, leading R&D centers in various countries, in the electronic design automation domain. Prior to joining Cadence Design Systems, Dr. Hanna was a Senior VP at Jasper Design Automation, which was acquired by Cadence in 2014. At Jasper, Dr. Hanna worked in the fast-emerging domain of formal verification technology and applications. Dr. Hanna was also an Intel Senior Principal Engineer and R&D Group Leader at Intel Haifa, where he was instrumental in the development of several generations of formal verification systems, which were used on almost all Intel microprocessor designs since early 1990s, and was twice the recipient of Intel’s highest Achievement Award (IAA). He received both his BS and MS degrees in Computer Science at Tel Aviv University, and his PhD in Computer Science from the University of Oxford. Besides his leadership at Cadence, Prof. Hanna is currently serving as a visiting professor of Computer Science at Oxford. Dr. Hanna is a senior IEEE member, holds over 15 patents, and has published more than 80 papers and talks.

Symmetric Is Better: Can We Exploit Regularities in Logic Synthesis? [Slides]
Valentina Ciriani, University of Milano, Italy

Abstract: The standard synthesis of Boolean functions is aimed at designing optimized circuits according to given cost criteria. For this purpose, the algebraic form of the function is manipulated, as it directly reflects the cost of the corresponding circuit. Depending on the design needs, different two-level or multi-level forms are considered, and ad hoc algorithms are used to express and minimize such forms. In all cases, the functions under consideration encode “real life” problems, hence they often exhibit a “regular” structure that can be exploited by synthesis algorithms. This talk aims to describe several function regularities based on the EXOR operator. Moreover, we show how these regularities can be exploited in logic synthesis for standard and emerging technologies. Finally, we show how regularities can also ease polynomial verification.

Valentina Ciriani received the Laurea degree and the Ph.D. degree in Computer Science from the University of Pisa, Italy, in 1998 and 2003, respectively. In 2003 and 2004 she was with the Department Computer Science at University Pisa, Italy as a Ph.D. fellow. From 2005 to 2015 she was an assistant professor in Computer Science at the Department of Computer Science, University of Milano, Italy. She is currently an Associate Professor in Computer Science with the Department of Computer Science of the University of Milano (Italy). Her research interests include algorithms and data structures, as well as combinational logic synthesis for classical and emerging technologies. She has authored or coauthored more than 100 research papers, published in international journals, conference proceedings, and books chapters.

Toward Software-to-Atoms Open-Source RISC-V Computing Platforms: Is Open-Source Synthesis Ready for Prime Time? [Slides]
Luca Benini, ETH Zurich / University of Bologna, Switzerland / Italy

Abstract: The success of the RISC-V free and open ISA has ushered us in the era Open-source computing hardware. As of today, open-source designs exist targeting a wide range of RISC-V based computing systems, from tiny microcontrollers to high-performance many-core, and industry adoption of open-source computing hardware is accelerating. However a key open question is if we can, or even should, push further, open sourcing design automation tools and technology libraries, PDKs, toward the vision of enabling "software-to-atoms" open source computing platforms. In this talk I will try assess where we stand and provide a personal view on key challenges and future trajectories, drawing from a decade of experience in designing and industrializing open source hardware.

Luca Benini holds the chair of digital Circuits and systems at ETHZ and is Full Professor at the Universita di Bologna. He received a PhD from Stanford University. Dr. Benini’s research interests are in energy-efficient parallel computing systems, smart sensing micro-systems and machine learning hardware. He is a Fellow of the IEEE, of the ACM and a member of the Academia Europaea. He is the recipient of the 2016 IEEE CAS Mac Van Valkenburg award, the 2020 EDAA achievement Award, the 2020 ACM/IEEE A. Richard Newton Award and the 2023 IEEE CS E.J. McCluskey Award.



Registration Is Open Now!!

Early registration deadline: May 27, 2024
Registration site

If needed, the VISA request information and instruction will be shown during the registration process.

If you are interested, kindly select the option for the "Post-workshop Social Event: Uetliberg Walk" in the registration form. Find the details of this event provided below.

Important Dates

Paper abstract submission: March 29, 2024 April 5, 2024 (AoE)
Full paper submission: April 5, 2024 April 12, 2024 (AoE)
Notification of acceptance: May 6, 2024 May 3, 2024
Final version due: May 31, 2024

Submission Instructions

Only complete papers with original and previously unpublished material are permitted. Submissions must be no longer than 8 pages (reference excluded), double column, 10-point font (we recommend using the ACM template or the IEEE template, but not necessary). Accepted papers are distributed only to IWLS participants.

Double-blind policy: IWLS uses a double-blind reviewing system. Manuscripts must not identify authors or their affiliations; those that do will not be considered.

If you have questions about how to meet these guidelines, please contact the program chairs before the submission deadline.

EasyChair IWLS 2024 submission page

IWLS Programming Contest

In 2022 and 2023, IWLS Programming Contest focused on synthesizing the smallest possible correct circuits for a suite of Boolean functions representative of hardware designs, including random logic, arithmetic operators, and typical functionality of artificial neurons in machine learning. This is the motivation to have this year’s competition closely resemble the last year’s competition when it comes to the rules, and only change the set of benchmarks used. As indicated in the IWLS 2023 Programming Contest announcement, we expect the participants to submit two sets of solutions, containing and-inverter graphs (AIGs) and xor-and-inverter graphs (XAIGs) for the given test cases. The results will be evaluated using the same criteria as in 2023.

We encourage the participant to carefully study the announcement of the past two competitions-which you can find in the official call for submissions-for other helpful information, including verification of the solutions using ABC.

IWLS 2024 Programming Contest Call for Submissions
IWLS 2024 Programming Contest Benchmarks

Submission site: IWLS 2024 Programming Contest Submission

Submission deadline: May 31, 2024 11:59 pm Anywhere on Earth
(Please note that the deadline is final and late submissions will not be considered!)

This year's programming contest prizes:
1st place: $800
2nd place: $400
3rd place: $300

Travel Information

Workshop venue

ETH Zurich, ETZ E6, Gloriastrasse 35, 8092 Zurich (map)

Nearby hotels

  1. Hotel Scheuble
  2. Hotel St. Josef
  3. Hotel Alexander Zurich
  4. Hotel Limmathof
Post-workshop Social Event: Uetliberg Walk

We are organizing a walk/light hike at Uetliberg mountain on Saturday, June 8th (the day after the workshop). This event is unofficially organized and the official registration fee does not cover public transportation costs. Nevertheless, please indicate your interest in the registration form for organizational purposes. The event will start at 10 am and end at approximately 6 pm; yet, there is a possibility to join later or leave early.

Schedule:

Participants are welcome to join for only part of the event, e.g., coming directly to the restaurant, meeting later, or leaving early. Several volunteers will attend the hike and can assist in local transportation.

Organizing Committee

General Chair Lana Josipović ETH Zurich
Program Committee Chairs Giulia Meuli / Winston Haaswijk Synopsys / Cadence
Program Contest Chairs Alan Mishchenko / Yukio Miyasaka UC Berkeley
Special Session Chair Eleonora Testa Synopsys
Finance Chair Cunxi Yu University of Maryland
Proceedings Chair Marcel Walter TU Munich
Publicity Chairs Siang-Yun Lee / Jiahui Xu EPFL / ETH Zurich
Local Arrangements Chair Carmine Rizzi ETH Zurich

Technical Program Committee

Luca Amaru  Synopsys, USA
Anna Bernasconi  UniversitĂ  di Pisa, Italy
Lei Chen  Huawei Noah’s Ark Lab, Hong Kong SAR
Zhufei Chu  Ningbo University, China
Valentina Ciriani  UniversitĂ  degli Studi di Milano, Italy
Petr FiĆĄer  CTU, Czech Republic
Winston Haaswijk  Cadence Design Systems, UK
Jie-Hong Roland Jiang  National Taiwan University, Taiwan
Lana Josipović  ETH Zurich, Switzerland
Attila Jurecska  Siemens EDA, USA
Victor Kravets  IBM, USA
Siang-Yun Lee  EPFL, Switzerland
Giulia Meuli  Synopsys, USA
Alan Mishchenko  UC Berkeley, USA
Walter Lau Neto  Synopsys, USA
Augusto Neutzling  Cadence Design Systems, UK
Stefan Nikolić  EPFL, Switzerland
Weikang Qian  Shanghai Jiao Tong University, China
Andre Reis  UFRGS, Brazil
Tsutomu Sasao  Meiji University, Japan
Herman Schmit  Google, USA
Bruno Schmitt  Nvidia, Switzerland
Mathias Soeken  Microsoft, USA
Eleonora Testa  Synopsys, USA
Tiziano Villa  UniversitĂ  degli Studi di Verona, Italy
Robert Wille  TU Munich & SCCH GmbH, Germany
Xiaoqing Xu  X, the moonshot factory, USA
Cunxi Yu  University of Maryland, USA

Benchmarks

The IWLS community maintains a set of logic synthesis benchmarks (IWLS'05 and EPFL), available in various formats.

Mailing List

Subscribe to the IWLS mailing list. (The list is hidden and only its administrator can post to it.)

Links to Past Workshops

IWLS 2023: June 5 - June 5, 2023, Lausanne, Switzerland

IWLS 2022: July 18 - July 22, 2022, Virtual

IWLS 2021: July 19 - July 22, 2021, Virtual

IWLS 2020: July 27 - July 30, 2020, Virtual

IWLS 2019: June 21 - June 23, 2019, Lausanne, Switzerland

IWLS 2018: June 23 - June 24, 2018, San Francisco, California

IWLS 2017: June 17 - June 18, 2017, Austin, Texas

IWLS 2016: June 10 - June 11, 2016, Austin, Texas

IWLS 2015: June 12 - June 13, 2015, Mountain View, California

IWLS 2014: May 30 - June 1, 2014, San Francisco, California

IWLS 2013: June 7 - June 8, 2013, Austin, Texas

IWLS 2012: June 1 - June 3, 2012, Berkeley, California

IWLS 2011: June 3 - June 5, 2011, San Diego, California

IWLS 2010: June 18 - June 20, 2010, Irvine, California

IWLS 2009: July 31 - August 2, 2009, Berkeley, California

IWLS 2008: June 4 - 6, 2008, Lake Tahoe, California

IWLS 2007: May 30 - June 1, 2007, San Diego, California

IWLS 2006: June 7 - 9, 2006, Vail, Colorado

IWLS 2005: June 8 - 10, 2005, Lake Arrowhead, California

IWLS 2004: June 2 - 4, 2004, Temecula Creek, California

IWLS 2003: May 28 - 30, 2003, Laguna Beach, California

IWLS 2002: June 4 - 7, 2002, New Orleans, Louisiana

IWLS 2001: June 12 - 15, 2001, Lake Tahoe, California

IWLS 2000: May 31 - June 2, 2000, Dana Point, California

Related Conferences

ICCAD: International Conference on Computer-Aided Design

DATE: Design, Automation and Test in Europe

ASPDAC: Asia and South Pacific Design Automation Conference

DAC: Design Automation Conference

ISPD: International Symposium on Physical Design

ISLPED: International Symposium on Low Power Electronics and Design

IWBDA: International Symposium on Bio-Design Automation