IWLS 2024

The International Workshop on Logic and Synthesis is the premier forum for research in synthesis, optimization, and verification of integrated circuits and systems. Research on logic synthesis for emerging technologies and for novel computing platforms, such as nanoscale systems and biological systems, is also strongly encouraged. The workshop encourages the early dissemination of ideas and results. The workshop accepts complete papers highlighting important new problems in the early stages of development, without providing complete solutions. The emphasis is on novelty and intellectual rigor.

Topics of interest include but are not limited to: hardware synthesis and optimization; software synthesis; hardware/software co-synthesis; power and timing analysis; testing, validation, and verification; synthesis for reconfigurable architectures; hardware compilation for domain-specific languages; and design experiences. Submissions on modeling, analysis, and synthesis for emerging technologies and platforms are particularly encouraged.

The workshop format includes paper presentations, invited talks, social lunch and dinner gatherings, and recreational activities.

🏆 Information Graph-Based Resubstitution For Networks of Look-Up Tables. Andrea Costamagna (EPFL), Alessandro Tempia Calvino (EPFL), Alan Mishchenko (UC Berkeley), and Giovanni De Micheli (EPFL)

🥇 1st place: NUP (Neapolis University Pafos). Daniil Averkov, Gregory Emdin, Mikhail Goncharov, Alexander S. Kulikov, Daniil Levtsov, Georgie Levtsov, Vsevolod Vaskin, Aleksey Vorobiev

🥈 2nd place: ALCom Lab (National Taiwan University and MediaTek). Yu-Hao Ko, Shao-Jui Wu, Jie-Hong Roland Jiang, Wei-Chen Chien

🥉 3rd place: USTC and Huawei (University of Science and Technology of China and Huawei). Qingyue Yang, Zhihai Wang, Lei Chen, Xing Li, Yiwen Wang, Mingxuan Yuan, Jianye Hao, Jie Wang, Bin Li, Yongdong Zhang, Feng Wu

IWLS 2024 keynote and special session slides are available—check out below and the technical program page!

The program consists of 6 regular paper sessions, 1 poster session, 3 keynotes, and 1 special session.

	Can AI Design and Verify Your Design? [Slides] Ziyad Hanna, Cadence Design Systems, Israel Abstract: In this talk, I will explore the significant impact of artificial intelligence (AI) in addressing the mounting complexity and demands within chip design domain. With an anticipated exponential growth in annual revenue reaching the trillion-dollar mark, driven by the rapid growth in key markets in 5G, Hyperscalers, autonomous vehicles, AI, and industrial IoT. The chip design market is trending into a fourfold increase in project volume with tenfold complexity. The current design and verification methodologies are lacking in capacity to meet this surge, highlighting the shortage of qualified engineers to meet the aggressive market demand. AI technologies stand at the forefront of transforming design and verification processes, offering unparalleled efficiency and cost-effective solutions to meet the escalating market needs. In this talk, I will address the inherent challenges in the chip design industry, analyze the current landscape of automation, machine learning (ML), and cutting-edge generative AI technologies. I will also discuss a strategic direction for harnessing AI to enhance design synthesis and verification, including the automatic generation of programs supported by natural language processing (NLP) and generative AI, the creation of temporal assertions from design specifications, the integration of high-level synthesis (HLS) and formal verification, and the exploration of the latest advancements in AI technologies for full design and verification flow for achieving the aggressive demand on performance, power and area. Furthermore, the presentation emphasizes the essence for collaborative initiatives between industry and academia to drive forward transformative advancements and innovations within the chip design and verification domain with AI. Ziyad Hanna, Ph.D., is currently a corporate VP at Cadence Design Systems (CDNS), and the general manager of Cadence Israel, leading R&D centers in various countries, in the electronic design automation domain. Prior to joining Cadence Design Systems, Dr. Hanna was a Senior VP at Jasper Design Automation, which was acquired by Cadence in 2014. At Jasper, Dr. Hanna worked in the fast-emerging domain of formal verification technology and applications. Dr. Hanna was also an Intel Senior Principal Engineer and R&D Group Leader at Intel Haifa, where he was instrumental in the development of several generations of formal verification systems, which were used on almost all Intel microprocessor designs since early 1990s, and was twice the recipient of Intel’s highest Achievement Award (IAA). He received both his BS and MS degrees in Computer Science at Tel Aviv University, and his PhD in Computer Science from the University of Oxford. Besides his leadership at Cadence, Prof. Hanna is currently serving as a visiting professor of Computer Science at Oxford. Dr. Hanna is a senior IEEE member, holds over 15 patents, and has published more than 80 papers and talks.
	Symmetric Is Better: Can We Exploit Regularities in Logic Synthesis? [Slides] Valentina Ciriani, University of Milano, Italy Abstract: The standard synthesis of Boolean functions is aimed at designing optimized circuits according to given cost criteria. For this purpose, the algebraic form of the function is manipulated, as it directly reflects the cost of the corresponding circuit. Depending on the design needs, different two-level or multi-level forms are considered, and ad hoc algorithms are used to express and minimize such forms. In all cases, the functions under consideration encode “real life” problems, hence they often exhibit a “regular” structure that can be exploited by synthesis algorithms. This talk aims to describe several function regularities based on the EXOR operator. Moreover, we show how these regularities can be exploited in logic synthesis for standard and emerging technologies. Finally, we show how regularities can also ease polynomial verification. Valentina Ciriani received the Laurea degree and the Ph.D. degree in Computer Science from the University of Pisa, Italy, in 1998 and 2003, respectively. In 2003 and 2004 she was with the Department Computer Science at University Pisa, Italy as a Ph.D. fellow. From 2005 to 2015 she was an assistant professor in Computer Science at the Department of Computer Science, University of Milano, Italy. She is currently an Associate Professor in Computer Science with the Department of Computer Science of the University of Milano (Italy). Her research interests include algorithms and data structures, as well as combinational logic synthesis for classical and emerging technologies. She has authored or coauthored more than 100 research papers, published in international journals, conference proceedings, and books chapters.
	Toward Software-to-Atoms Open-Source RISC-V Computing Platforms: Is Open-Source Synthesis Ready for Prime Time? [Slides] Luca Benini, ETH Zurich / University of Bologna, Switzerland / Italy Abstract: The success of the RISC-V free and open ISA has ushered us in the era Open-source computing hardware. As of today, open-source designs exist targeting a wide range of RISC-V based computing systems, from tiny microcontrollers to high-performance many-core, and industry adoption of open-source computing hardware is accelerating. However a key open question is if we can, or even should, push further, open sourcing design automation tools and technology libraries, PDKs, toward the vision of enabling "software-to-atoms" open source computing platforms. In this talk I will try assess where we stand and provide a personal view on key challenges and future trajectories, drawing from a decade of experience in designing and industrializing open source hardware. Luca Benini holds the chair of digital Circuits and systems at ETHZ and is Full Professor at the Universita di Bologna. He received a PhD from Stanford University. Dr. Benini’s research interests are in energy-efficient parallel computing systems, smart sensing micro-systems and machine learning hardware. He is a Fellow of the IEEE, of the ACM and a member of the Academia Europaea. He is the recipient of the 2016 IEEE CAS Mac Van Valkenburg award, the 2020 EDAA achievement Award, the 2020 ACM/IEEE A. Richard Newton Award and the 2023 IEEE CS E.J. McCluskey Award.

Registration Is Open Now!!

If needed, the VISA request information and instruction will be shown during the registration process.

If you are interested, kindly select the option for the "Post-workshop Social Event: Uetliberg Walk" in the registration form. Find the details of this event provided below.

Paper abstract submission:		~~March 29, 2024~~ April 5, 2024 (AoE)
Full paper submission:		~~April 5, 2024~~ April 12, 2024 (AoE)
Notification of acceptance:		~~May 6, 2024~~ May 3, 2024
Final version due:		May 31, 2024

Only complete papers with original and previously unpublished material are permitted. Submissions must be no longer than 8 pages (reference excluded), double column, 10-point font (we recommend using the ACM template or the IEEE template, but not necessary). Accepted papers are distributed only to IWLS participants.

Double-blind policy: IWLS uses a double-blind reviewing system. Manuscripts must not identify authors or their affiliations; those that do will not be considered.

If you have questions about how to meet these guidelines, please contact the program chairs before the submission deadline.

In 2022 and 2023, IWLS Programming Contest focused on synthesizing the smallest possible correct circuits for a suite of Boolean functions representative of hardware designs, including random logic, arithmetic operators, and typical functionality of artificial neurons in machine learning. This is the motivation to have this year’s competition closely resemble the last year’s competition when it comes to the rules, and only change the set of benchmarks used. As indicated in the IWLS 2023 Programming Contest announcement, we expect the participants to submit two sets of solutions, containing and-inverter graphs (AIGs) and xor-and-inverter graphs (XAIGs) for the given test cases. The results will be evaluated using the same criteria as in 2023.

Submission deadline: May 31, 2024 11:59 pm Anywhere on Earth
(Please note that the deadline is final and late submissions will not be considered!)

This year's programming contest prizes:

1^st place:		$800
2^nd place:		$400
3^rd place:		$300

Workshop venue

Nearby hotels

We are organizing a walk/light hike at Uetliberg mountain on Saturday, June 8th (the day after the workshop). This event is unofficially organized and the official registration fee does not cover public transportation costs. Nevertheless, please indicate your interest in the registration form for organizational purposes. The event will start at 10 am and end at approximately 6 pm; yet, there is a possibility to join later or leave early.

Participants are welcome to join for only part of the event, e.g., coming directly to the restaurant, meeting later, or leaving early. Several volunteers will attend the hike and can assist in local transportation.

General Chair	Lana Josipović	ETH Zurich
Program Committee Chairs	Giulia Meuli / Winston Haaswijk	Synopsys / Cadence
Program Contest Chairs	Alan Mishchenko / Yukio Miyasaka	UC Berkeley
Special Session Chair	Eleonora Testa	Synopsys
Finance Chair	Cunxi Yu	University of Maryland
Proceedings Chair	Marcel Walter	TU Munich
Publicity Chairs	Siang-Yun Lee / Jiahui Xu	EPFL / ETH Zurich
Local Arrangements Chair	Carmine Rizzi	ETH Zurich

Luca Amaru		Synopsys, USA
Anna Bernasconi		Università di Pisa, Italy
Lei Chen		Huawei Noah’s Ark Lab, Hong Kong SAR
Zhufei Chu		Ningbo University, China
Valentina Ciriani		Università degli Studi di Milano, Italy
Petr Fišer		CTU, Czech Republic
Winston Haaswijk		Cadence Design Systems, UK
Jie-Hong Roland Jiang		National Taiwan University, Taiwan
Lana Josipović		ETH Zurich, Switzerland
Attila Jurecska		Siemens EDA, USA
Victor Kravets		IBM, USA
Siang-Yun Lee		EPFL, Switzerland
Giulia Meuli		Synopsys, USA
Alan Mishchenko		UC Berkeley, USA
Walter Lau Neto		Synopsys, USA
Augusto Neutzling		Cadence Design Systems, UK
Stefan Nikolić		EPFL, Switzerland
Weikang Qian		Shanghai Jiao Tong University, China
Andre Reis		UFRGS, Brazil
Tsutomu Sasao		Meiji University, Japan
Herman Schmit		Google, USA
Bruno Schmitt		Nvidia, Switzerland
Mathias Soeken		Microsoft, USA
Eleonora Testa		Synopsys, USA
Tiziano Villa		Università degli Studi di Verona, Italy
Robert Wille		TU Munich & SCCH GmbH, Germany
Xiaoqing Xu		X, the moonshot factory, USA
Cunxi Yu		University of Maryland, USA

The IWLS community maintains a set of logic synthesis benchmarks (IWLS'05 and EPFL), available in various formats.

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