2025 |
34th International Workshop on Logic & Synthesis June 12–13, 2025 University of Verona, Verona, Italy
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Our sponsors
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| IWLS 2025 Technical Program |
Link to the workshop proceedings
| Thursday June 12 | ||
| 9:00–9:10: Welcome coffee | ||
| 9:10–9:20: Opening session | Opening | |
| 9:20–10:20: Keynote | Keynote 1 (Chair: Tiziano Villa) | |
| Tsetlin Machines: Towards Energy-Efficient and Explainable AI via Logic and Expediency in Learning | Alex Yakovlev (Newcastle University) | |
| 10:20–11:00: Paper session | Session 1: Approximate Logic Synthesis (Chair: Petr Fišer) | |
| 7 | QUADOL: A Quality-Driven Approximate Logic Synthesis Method Exploiting Dual-Output LUTs for Modern FPGAs. Best student paper candidate | Jian Shi, Xuan Wang, Chang Meng and Weikang Qian |
| 23 | Simulation-Guided Approximate Logic Synthesis Under the Maximum Error Constraint | Chang Meng, Weikang Qian and Giovanni De Micheli |
| 11:00–11:30: Coffee Break | ||
| 11:30–12:50: Paper session | Session 2: Core Logic Optimization Techniques (Chair: Zhufei Chu) | |
| 27 | Ashenhurst-Curtis Decomposition Using Don't Cares | Benjamin Hien, Marcel Walter, Alessandro Tempia Calvino, Alan Mishchenko and Robert Wille |
| 9 | Scalable Framework for Redundancy Analysis and Logic Optimization | Yukio Miyasaka, Alan Mishchenko and John Wawrzynek |
| 18 | Versatile Rewiring and Concurrent Resynthesis for High-Quality Customized Optimization |
Jiun-Hao Chen, Jie-Hong Roland Jiang and Alan Mishchenko |
| 22 | Search-Space Exploration Guided by Functional AIG Classification | Benjamin Ihme, Siang-Yun Lee and Heinz Riener |
| 12:50–14:00: Lunch | ||
| 14:00–15:00: Keynote | Keynote 2 (Chair: Anna Bernasconi) | |
| High-Level Synthesis: Transforming the Design of Heterogeneous System-on-Chips | Marcello Dusini, Gianluca Rigano, and David Vincenzoni (STMicroelectronics) | |
| 15:00–15:40: Paper session | Session 3: Synthesis and Verification for Logic-in-Memory (Chair: Cunxi Yu) | |
| 28 | veriSiM: Formal Verification of Spice Netlists for MAGIC-Based Logic-in-Memory | Chandan Kumar Jha, Simranjeet Singh, Khushboo Qayyum, Ankit Bende, Muhammad Hassan, Vikas Rana, Farhad Merchant and Rolf Drechsler |
| 10 | High-Quality Iterative Logic Compiler for In-Memory SIMD Computation with Tight Coupling of Synthesis and Scheduling. Best student paper candidate | Xingyue Qian, Chenyang Lv, Zhezhi He and Weikang Qian |
| 15:40–16:10: Poster & coffee | Posters 5, 15, 37, and 38 | |
| 5 | CCubes: a quasi-polynomial, exact Boolean minimizer | Adrian Dusa and Paul Irofti |
| 15 | A Design of Compressor Trees for LLM Module | Tsutomu Sasao and Alan Mishchenko |
| 37 | A Didactic Diagnosis Tool to Catalog Errors in Sum-Of-Products | Leonardo Droves Silveira, Renato Peralta, Jordi Cortadella and Andre Reis |
| 38 | Minecraft and Roblox as tools to teach Digital Circuit Design: an analysis of the state of the art | Marcelo Almeida da Silva, Renato Peralta, Alcides Costa and Andre Reis |
| 16:10–17:30: Paper session | Session 4: Advanced Logic Synthesis Methods (Chair: Winston Haaswijk) | |
| 4 | Promise: Property Mining for Sequential Synthesis | Jiahui Xu, Jordi Cortadella and Lana Josipovic |
| 6 | GradMap: A Gradient-Descent Approach to Load-Dependent Technology Mapping | Hsin-Ying Tsai, Chung-Kai Wu, Chih-Cheng Hsu and Jie-Hong Roland Jiang |
| 24 | Molecular Dynamics In Mapped Networks For Placement-Aware Resynthesis | Andrea Costamagna, Chang Meng and Giovanni De Micheli |
| 21 | Boolean Reasoning Guided Ungrouping | Giulia Meuli, Eleonora Testa, Elena Teica, Alan Vaz, Vishal F. Aralikatti, Abhishek Kumar, Brian Lockyear and Luca Amaru |
| Dinner at Ristorante Torcolo (Via Carlo Cattaneo, 11, Verona) We meet up at the restaurant between 7:30 pm - 8:00 pm; the dinner starts at 8:00 pm |
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| Friday June 13 | ||
| 9:00–9:10: Welcome coffee | ||
| 9:10–10:10: Keynote | Keynote 3 (Chair: Valentina Ciriani) | |
| Stronger Together: Bridging Logic Synthesis and Side-Channel Analysis | Elena Dubrova (Royal Institute of Technology KTH) | |
| 10:10–10:50: Paper session | Session 5: Design of Advanced Multipliers (Chair: Jie-Hong Roland Jiang) | |
| 16 | HiPeR-SM: High Performance Reconfigurable Scalar Multiplier over NIST-P256 and CURVE25519 | Rushikesh Kawale, Sonali Shukla, Makoto Ikeda, Masahiro Fujita and Virendra Singh |
| 26 | Explicit Sign-Magnitude Encoders Enable Power-Efficient Multipliers | Felix Arnold, Maxence Bouvier, Ryan Amaudruz, Renzo Andri and Lukas Cavigelli |
| 10:50–11:20: Coffee Break | ||
| 11:20–12:40: Paper session | Session 6: Machine Learning for Logic Synthesis and Verification (Chair: Chandan Kumar Jha) | |
| 19 | Circuit Learning for Multi-Output Boolean Functions. Best student paper candidate | Jiun-Hao Chen and Jie-Hong Roland Jiang |
| 25 | ReVEAL: Reverse Engineering of Multiplier Architectures via Graph Learning for Computer Algebra Verification | Chen Chen, Daniela Kaufmann, Chenhui Deng, Hongce Zhang and Cunxi Yu |
| 30 | ML-Inspired Logic Synthesis: Improving Multiplier Circuits | Yukio Miyasaka, Walter Lau Neto, Eleonora Testa, Anika Prasad, Michael Shuster, Reto Zimmermann, Patrick Vuillod, Alan Mishchenko, John Wawrzynek and Luca Amaru |
| 33 | GNN-NPN: Efficient NPN Classification for Large Functions using Graph Neural Network | Chengdi Cao, Hanyu Wang, Wan-Hsuan Lin and Jason Cong |
| 12:40–12:55: Benchmark session | EPFL Benchmark Results Update | |
| 12:55–14:00: Lunch | ||
| 14:00–14:40: Paper session | Session 7: Analysis and Synthesis for FPGA (Chair: Chang Meng) | |
| 14 | Statistical Method to Estimate the Number of LUTs to Realize Sparse Logic Functions | Tsutomu Sasao |
| 28 | FPGA Synthesis of ABM and EFORK Methods to Emulate Frational Order Chaotic Oscillators | Ramon Ulises Almada Prieto, Gilberto Enrico Vazquez Alcaraz, Opeyemi Micheal Afolabi and Jose Cruz Nunez Perez |
| 14:40–15:10: Contest session | Programming Contest Award (Alan Mishchenko) | |
| 15:10–15:40: Poster & coffee | Posters 12, 17, 29, 36, and 39 | |
| 12 | Approximate Maximum Common Subgraph Search in Large Digital Circuits via Smart Heuristic | Paolo Bernardi, Lorenzo Cardone and Stefano Quer |
| 17 | Faster and Better: AIG Depth Reduction for Timing Optimization | Siang-Yun Lee and Heinz Riener |
| 29 | Efficient Timing Optimization for Logic Synthesis | Felipe Marranghello, Walter Lau Neto, Patrick Vuillod and Luca Amaru |
| 36 | Neuralis: Verilog design analysis and correction using LLMs | Alcides Costa, Leonardo Droves Silveira, Renato Peralta and Andre Reis |
| 39 | Revisiting a Classic Algorithm for Automatic Generation of Standard Cells | Andrews Rodrigues, Paulo Butzen, Felipe Bortolon and Andre Reis |
| 15:40–17:00: Paper session | Session 8: Logic Synthesis and Analysis for Specialized Targets (Chair: Giulia Meuli) | |
| 20 | Application of Logic Synthesis to Accelerate SAT-solving | Jan Kimr and Petr Fišer |
| 35 | A Comprehensive Multibit Optimization Algorithm | Xuchu Hu, Reto Zimmermann, Sandeep Kumar and Luca Gaetano Amaru |
| 13 | Scalable Constant Division: Truth Table Compression Approach | Danila Gorodecky |
| 31 | XOR Identification in And-Inverter Graphs Using Functional Analysis | Yu-Hao Ko, Jie-Hong Roland Jiang and Thomas Li |
| 17:00–17:30: Closing session | Closing Session & Best Paper Award | |
| Saturday June 14 | ||
| Visit to the exhibition on the works of Fra Giovanni da Verona, Via Cantarane, 24 - Verona at 10 am. | ||