Mission: The International Workshop on Logic and Synthesis is dedicated to research in synthesis, optimization, and verification of integrated circuits. Research on logic synthesis for emerging technologies and for novel computing platforms, such as nanoscale systems and biological systems, is also strongly encouraged. The workshop accepts complete papers as well as abstracts highlighting important new problems in the early stages of development. The emphasis is on novelty and intellectual rigor.
Call for Participation (please post/distribute).The International Workshop on Logic and Synthesis is the premier forum for research in synthesis, optimization, and verification of integrated circuits. Research on logic synthesis for emerging technologies and for novel computing platforms, such as nanoscale systems and biological systems, is also strongly encouraged. The workshop accepts complete papers as well as abstracts, highlighting important new problems in the early stages of development, without providing complete solutions. The emphasis is on novelty and intellectual rigor.Topics of interest include (but are not limited to): synthesis and optimization; power and timing analysis; testing, validation and verification; architectures and compilation; and design experiences. Submissions on modeling, analysis and synthesis for emerging technologies and platforms are also encouraged. Both complete papers as well as extended abstracts highlighting new problems and new topics of research are welcomed. Only original and previously unpublished material is permitted. Accepted papers are distributed only to IWLS participants. The workshop format includes paper presentations, posters, invited talks, social lunch and dinner gatherings, and recreational activities.
The technical program consists of 21 regular talks, 3 invited talks, 1 special session and 4 poster presentations. The workshop will be held in Room 1202 at the University of California - San Diego, Computer Science and Engineering Department, Building EBU3B.
Invited talks:
Special Session: Novel Applications of Reconfigurable Logic Circuits
Rates for registration on or before May 9, 2011:
Rates for late registration (effective May 10, 2011):
The cost of registration includes breakfasts, lunches, dinners and coffee break service. Registration to IWLS does include entrance to the DAC Exhibit Hall Monday through Wednesday and all four Keynote addresses. An additional registration option is available if you wish to attend DAC Technical Sessions and additional fees are incurred. Please also note that a DAC Conference Registration does not include colocated conferences. You must go to the DAC registration page in order to register for IWLS. Please follow the instructions below to register:
The hotel address is: Clarion Del Mar Inn, 720 Camino Del Mar, Del Mar, CA 92014. Email contact: sales@delmarinn.com
The IWLS community maintains a set of benchmarks, synthesized and mapped in Verilog and OpenAccess.
IWLS 2010: June 18 - June 20, 2010, Irvine, California IWLS 2009: July 31 - August 2, 2009, Berkeley, California IWLS 2008: June 4 - 6, 2008, Lake Tahoe, California IWLS 2007: May 30 - June 1, 2007, San Diego, California IWLS 2006: June 7 - 9, 2006, Vail, Colorado IWLS 2005: June 8 - 10, 2005, Lake Arrowhead, California IWLS 2004: June 2 - 4, 2004, Temecula Creek, California IWLS 2003: May 28 - 30, 2003, Laguna Beach, California IWLS 2002: June 4 - 7, 2002, New Orleans, Louisiana IWLS 2001: June 12 - 15, 2001, Lake Tahoe, California IWLS 2000: May 31 - June 2, 2000, Dana Point, California
Subscribe to the IWLS mailing list. (The list is hidden, and only its administrator can post to it.)
|