Co-located with the
Design Automation Conference

24th International Workshop
on Logic & Synthesis

June 12 – 13, 2015

Computer History Museum — Mountain View, CA
Computer History Museum

Our sponsors


The International Workshop on Logic and Synthesis is the premier forum for research in synthesis, optimization, and verification of integrated circuits and systems. Research on logic synthesis for emerging technologies and for novel computing platforms, such as nanoscale systems and biological systems, is also strongly encouraged. The workshop encourages early dissemination of ideas and results. The workshop accepts complete papers highlighting important new problems in the early stages of development, without providing complete solutions. The emphasis is on novelty and intellectual rigor.

Call for Papers

Call for Papers in PDF

Topics of interest include, but are not limited to: hardware synthesis and optimization; software synthesis; hardware/software co-synthesis; power and timing analysis; testing, validation and verification; synthesis for reconfigurable architectures; hardware compilation for domain-specific languages; design experiences. Submissions on modeling, analysis and synthesis for emerging technologies and platforms are particularly encouraged.

The workshop format includes paper presentations, posters, invited talks, social lunch and dinner gatherings, and recreational activities. Accepted papers are distributed exclusively to IWLS participants.

Technical Program

The technical program consists of 16 regular talks, 6 posters and 3 keynotes. A visit to the Museum is currently planned for Friday June 12 evening.


EDA 3.0 [slides]
Leon Stok, IBM

Why does it take about 3 seconds to look up the shortest path from my home to JFK, and does it take a couple of hours to find the critical path in a large chip in an advanced technology? Are the engineers working on Google maps that much smarter than the engineers in the EDA industry or is there something else at work? Do they have access to much more intelligent and faster algorithms than anybody in EDA ever thought off? Do EDA design tools have to handle that much more data on a chip than the data that has been accumulated in maps or is design data that much more dynamic than a fairly static map of roads?
This presentation will take a first step to answering these questions and spawn a discussion on a new way to implement EDA tools and deliver them in integrated design flows to the market.

Leon Stok is Vice President of IBM's Electronic Design Automation group. Prior to this he held positions as director of EDA and executive assistant to IBM's Senior Vice President of Technology and Intellectual Property and executive assistant to IBM's Senior Vice President of the Technology group.Leon Stok studied electrical engineering at Eindhoven University of Technology, the Netherlands, from which he graduated with honors in 1986. He obtained a Ph.D. degree from Eindhoven University in 1991. Leon Stok worked at IBM's Thomas J. Watson Research Center as part of the team that developed BooleDozer, the IBM logic synthesis tool. Subsequently he managed IBM's logic synthesis group and drove the development of PDS, IBM’s Placement Driven Synthesis tool. From 1999-2004 he lead all of IBM's design automation research as the Senior Manager Design Automation at IBM Research.Mr. Stok has published over sixty papers on many aspects of high level, architectural and logic synthesis, low power design, placement driven synthesis and on the automatic placement and routing for schematic diagrams. He holds 8 patents in the area of EDA. He was elected an IEEE fellow for the development and application of high-level and logic synthesis algorithms.

An Introduction to Algorithmic Trading
Satrajit Chatterjee, Two Sigma

In this talk, I'll be presenting an overview of modern markets in terms of the nature of participants and the factors influencing their evolution. A significant portion of the talk will focus on the general architecture of algorithmic trading systems and the engineering challenges faced in building these systems. No prior knowledge of finance will be assumed and questions and digressions will be very welcome.

Satrajit Chatterjee is a Senior Vice President at Two Sigma Securities, where he leads a number of different efforts spanning various aspects of algorithmic trading, ranging from proprietary trading algorithms to the design and implementation of low latency trading systems. Before joining Two Sigma, he was a researcher at the Intel's Strategic CAD Labs, where he worked on high-level modeling, formal verification and synthesis of on-chip networks for memory access and cache coherence for servers and Systems-on-Chip. He has a PhD in Computer Science from Berkeley, where his focus was on efficient algorithms for logic synthesis and formal verification.

Physical Synthesis 2.0 [slides]
Andrew Kahng, UCSD

Separation of logical, temporal and spatial concerns during RTL-down implementation has always been fundamentally at odds with having a predictable, one-pass implementation flow. Over the past 20+ years, “layout-aware” logic synthesis, aka “physical synthesis”, has grudgingly relaxed this separation, lessening unpredictability by doing “spatial embedding under the hood”. Today’s physical synthesis faces many challenges: (i) FinFET discreteness and drive current; (ii) wire resistivity and dominance at high-performance corners; (iii) sensitivity of power, area and timing to endpoint constraints and congestion; and many other trends. Are new techniques and mindsets available for a “physical synthesis 2.0” renewal? Or is logic synthesis simply hanging on until the physics of gates and wires flip the switch to “logic-aware layout”?

Andrew B. Kahng is Professor of CSE and ECE at UC San Diego, where he holds the endowed chair in High-Performance Computing. He has served as visiting scientist at Cadence (1995-1997) and as founder, chairman and CTO at Blaze DFM (2004-2006). He is the coauthor of 3 books and over 400 journal and conference papers, holds 29 issued U.S. patents, and is a fellow of ACM and IEEE. He has served as general chair of DAC, ISQED, ISPD and other conferences. He is also international chair and co-chair of the Design technology working group, and recently of the System Integration focus team, in the ITRS since 2000. His research interests include IC physical design and performance analysis, the IC design-manufacturing interface, combinatorial algorithms and optimization, and the roadmapping of systems and technology.


    Until May 12   From May 13
ACM/IEEE members:   Students   $200   $300
  Others   $350   $450
Non ACM/IEEE members:   Students   $300   $400
  Others   $500   $650

The cost of registration includes breakfasts, lunches, social event and coffee break service.

Register for IWLS on the DAC registration page following the instructions below:

  1. Go to https://reg.mpassociates.com/reglive/PromoCode.aspx?confid=182 and click on "Register". This will direct you to the registration page.
  2. Complete all the contact information and enter your membership status. Click "Select Your Participation". This will bring you to the product choice page.
  3. Open the "Colocated Conferences" tab, select the IWLS option, and click on "Checkout" to proceed to checkout.
For any question regarding the registration process, please email Register@dac.com or call the DAC offices at +1-303-530-4333.

Hotel and Transportation

Here is a list of hotels near the computer history museum. Concerning transportation, we advise the following options:

  1. Consider renting a car, it can be the most comfortable option for you. In the case you decide otherwise, see the following two options.
  2. Choose a hotel nearby, in a radius of 5 miles from the museum and we can organize a shared ride. Maybe the hotel can offer a free shuttle to the museum (ask for it).
  3. Optionally, we can pick-up a limited number of people at the Caltrain Station in Mountain View. Then you have to use the triplanner available here to plan your trip in order to arrive in Mountain View Caltrain Station with sufficient time in advance.
If you have any difficulty regarding hotel and transportation, please contact André Reis (andre.reis at inf.ufrgs.br).

Important Dates

It is mandatory to register a paper by submitting an abstract before the deadline below.

Paper abstract submission: March 14, 2015
Full paper submission: March 20, 2015 @ 11.59pm Anywhere on Earth
Notification of acceptance: April 17, 2015
Final version due: May 8, 2015

The submission deadline is final. There will be no extension.

Submission instructions

Only complete papers with original and previously unpublished material are permitted. Submissions must be no longer than 8 pages, double column, 10-point font. Accepted papers are distributed only to IWLS participants.

EasyChair IWLS 2015 submission page

Resources for Students
Provided by the Technical Committee on VLSI (TCVLSI) from IEEE Computer Society

Best Student Paper Award: IWLS 2015 will be giving a Best Student Paper Award to a work of outstanding quality presented at the Workshop whose first author is a student. The award consists of US$ 100 and a certificate.
Student Travel Grants: IWLS 2015 will be giving two travel grants of US$ 250 for students. Applications were accepted until May 12

Please, contact Leomar Rosa Jr (leomarjr at inf.ufpel.edu.br) if you have any question regarding student travel grants.

Organizing Committee

General Chair André Reis UFRGS, Brazil
Program Committee Chair Dirk Stroobandt Ghent University, Belgium
Special Sessions Chair Gang Qu University of Maryland, US
Publicity Chair Mihir Choudhury IBM, US
Finance Chair Leomar Rosa Jr UFPel, Brazil

Steering Committee

Ilya Wagner Intel, US
Valeria Bertacco University of Michigan, US
Philip Brisk University of California Riverside, US
Stephen A. Edwards Columbia University, US
Alan Mishchenko University of California Berkeley, US

Technical Program Committee