Co-located with the
Design Automation Conference

25th International Workshop
on Logic & Synthesis

June 10 – 11, 2016

Thompson Conference Center — Austin, TX

Thompson Conference Center

Our sponsors


The International Workshop on Logic and Synthesis is the premier forum for research in synthesis, optimization, and verification of integrated circuits and systems. Research on logic synthesis for emerging technologies and for novel computing platforms, such as nanoscale systems and biological systems, is also strongly encouraged. The workshop encourages early dissemination of ideas and results. The workshop accepts complete papers highlighting important new problems in the early stages of development, without providing complete solutions. The emphasis is on novelty and intellectual rigor.

Call for Papers

Call for Papers in PDF

Topics of interest include, but are not limited to: hardware synthesis and optimization; software synthesis; hardware/software co-synthesis; power and timing analysis; testing, validation and verification; synthesis for reconfigurable architectures; hardware compilation for domain-specific languages; design experiences. Submissions on modeling, analysis and synthesis for emerging technologies and platforms are particularly encouraged.

The workshop format includes paper presentations, posters, invited talks, social lunch and dinner gatherings, and recreational activities. Accepted papers are distributed exclusively to IWLS participants.

Technical Program

The technical program consists of 16 regular talks, 6 posters, 2 keynotes and 1 special session.


Amorphous Data-parallelism
Keshav Pingali, UT Austin

Although data-parallelism is ubiquitous in high-performance computing (HPC) algorithms, many algorithms in other areas such as graph analytics, machine learning, and VLSI placement and routing exhibit a more complex kind of parallelism that called "amorphous data-parallelism."
In this talk, I describe a simple programming model called the operator formulation of algorithms for specifying amorphous data-parallelism, and a system called Galois for exploiting amorphous data-parallelism. Experimental results show that this is a practical approach for exploiting parallelism in complex, irregular applications that are beyond the capabilities of current commercial systems.

Keshav Pingali is a Professor in the Department of Computer Science at the University of Texas at Austin, and he holds the W.A."Tex" Moncrief Chair of Computing in the Institute for Computational Engineering and Sciences (ICES) at UT Austin.
Pingali is a Fellow of the IEEE, ACM and AAAS. He was the co-Editor-in-chief of the ACM Transactions on Programming Languages and Systems, and currently serves on the editorial boards of the ACM Transactions on Parallel Computing, the International Journal of Parallel Programming and Distributed Computing. He has also served on the NSF CISE Advisory Committee (2009-2012).

Design Automation Challenges in Neuromorphic Systems
Rajit Manohar, Cornell University

Neuromorphic systems are an emerging class of programmable substrates inspired by biological neural networks. These systems are typically implemented using a combination of analog and asynchronous digital components, and recent work has shown how they can be used for low power implementation of neural-network based machine learning algorithms. This talk provides an abbreviated history of the field, and describes our recent work with IBM on an all-digital approach to neuromorphic system engineering that culminated in TrueNorth--a low-power single chip million neuron system. We discuss some of the automation challenges that we faced in the design of such systems, as well as in improving the usability of neuromorphic systems.

Rajit Manohar is Professor of Electrical and Computer Engineering and a Weiss Presidential Fellow at Cornell. He received his B.S. (1994), M.S. (1995), and Ph.D. (1998) from Caltech. He has been on the Cornell faculty since 1998 and the Cornell Tech faculty since 2012, where his group conducts research on self-timed systems. He is the recipient of an NSF CAREER award, nine best paper awards, seven teaching awards, and was named to MIT technology review's top 35 young innovators under 35 for contributions to low power microprocessor design.

Special Session on Emerging Technologies

Biochemistry Synthesis on Digital Microfluidic Biochips
Krishnendu Chakrabarty, Duke University

Advances in microfluidics have led to the emergence of biochips for automating laboratory procedures in molecular biology. These devices enable the precise control of nanoliter volumes of biochemical samples and reagents. This talk will first introduce electrowetting-based digital microfludic biochips and provide an overview of market drivers such as immunoassays and DNA sequencing. Next, synthesis tools will be described to map bioassay protocols from the lab bench to a droplet-based microfluidic platform. The role of the digital microfluidic biochip as a “programmable and reconfigurable processor” for biochemical applications will be highlighted. Finally, the speaker will describe dynamic adaptation of bioassays through cyberphysical system integration and sensor-driven on-chip error recovery, as well as recent advances in utilizing cyberphysical integration for quantitative gene-expression analysis.

Krishnendu Chakrabarty received the B. Tech. degree from the Indian Institute of Technology, Kharagpur, in 1990, and the M.S.E. and Ph.D. degrees from the University of Michigan, Ann Arbor, in 1992 and 1995, respectively. He is now the William H. Younger Distinguished Professor of Engineering in the Department of Electrical and Computer Engineering at Duke University. Prof. Chakrabarty is a recipient of the National Science Foundation Early Faculty (CAREER) award, the Office of Naval Research Young Investigator award, the Humboldt Research Award from the Alexander von Humboldt Foundation, Germany, the IEEE Transactions on CAD Donald O. Pederson Best Paper award (2015), 11 best paper awards at major IEEE conferences, and numerous further awards. Prof. Chakrabarty’s current research projects include, besides others, digital microfluidics, biochips, and cyberphysical systems. He served for many major journals and conferences such as JETC, ICCAD, DAC, etc.

Photonic Design Automation: Old Wine in New Bottle?
Priyank Kalla, University of Utah

Recent breakthroughs in silicon photonic technology are enabling the integration of optical devices into silicon-based semiconductor processes. This is motivating investigations into applications beyond that of traditional telecom: sensing, filtering, signal processing, quantum technology -- and even optical computing. In effect, we are now seeing a convergence of communications and computation, where the traditional roles and boundaries of optics and microelectronics are becoming blurred. Photonic design automation represents an opportunity to take opto-electronic integrated circuit design to a larger scale, facilitating design-space exploration, and laying the foundation for current and future optical applications -- thus fully realizing the potential of this technology.
In this talk, I will describe our work on design automation for integrated optic systems. Using a building-block model for optical devices, we provide an EDA-inspired design flow and synthesis algorithms for optical design automation. I will show how the resulting synthesis problems can be formulated in terms of classical logic and physical synthesis formalisms -- e.g., Boolean function decomposition, technology mapping, global and channel routing, thermal-aware (re)synthesis, etc. I will describe our CAD tool development efforts, which actually resulted in the design of an optical logic chip which was fabricated through the OpSIS program.

Priyank Kalla is an Associate Professor in the Electrical & Computer Engineering department at the Univ. of Utah. His areas of interests are in electronic design automation and hardware verification. He received the B.E. degree in Electronics from Sardar Patel University in India (1993) and M.S. and Ph.D. from the Univ. of Massachusetts Amherst in 1998 and 2002, respectively. He has worked with AMD K-7 and the DEC Alpha microprocessor CAD & Test groups. He's a recipient of the US NSF CAREER award and the ACM Trans. on Design Automation best paper award. He was the chair of IEEE technical committee on computer-aided network design and currently also serves as an associate editor for IEEE Trans. on CAD.

Reversible Circuits: Application and Design Challenges
Rolf Drechsler, University of Bremen/DFKI GmbH, Germany

Reversible circuits build the basis for emerging technologies like quantum computation and have promising applications in domains like low power design. Because of that, much progress in the development of design solutions for this kind of circuits has been made in the last decade. This talk provides an overview on reversible circuits and a selection of their most promising applications. Afterwards, it is shown how the design of corresponding reversible circuits differ from conventional EDA problems and recent solutions which address the corresponding challenges are presented.

Rolf Drechsler received the Diploma and Dr. phil. nat. degrees in computer science from the J. W. Goethe University Frankfurt am Main, Frankfurt am Main, Germany, in 1992 and 1995, respectively. He was with the Institute of Computer Science, Albert-Ludwigs University, Freiburg im Breisgau, Germany and with the Corporate Technology Department, Siemens AG, Munich, Germany. Since October 2001, he has been with the University of Bremen, Bremen, Germany, where he is currently a Full Professor and the Head of the Group for Computer Architecture, Institute of Computer Science. Since 2011, he is also the Director of the Cyber-Physical Systems group at the German Research Center for Artificial Intelligence (DFKI) in Bremen. His research interests include the development and design of data structures and algorithms with a focus on circuit and system design. In these areas, he published more than 250 papers and served in program committees of international conferences such as DAC, DATE, and ICCAD.


    Until May 11   From May 12
ACM/IEEE members:   Students   $200   $300
  Others   $350   $450
Non ACM/IEEE members:   Students   $300   $400
  Others   $/500   $650

The cost of registration includes breakfasts, lunches, social event and coffee break service.

Register for IWLS on the DAC registration page following the instructions below:

If you are not registered at DAC:

  1. Go to https://reg.mpassociates.com/reglive/PromoCode.aspx?confid=200 and click on "Register". This will direct you to the registration page.
  2. Complete all the contact information and enter your membership status. Click "Select Your Participation". This will bring you to the product choice page.
  3. Open the "Colocated Conferences" tab, select the IWLS option, and click on "Checkout" to proceed to checkout.

If you are registered at DAC and would like to add an IWLS registration:

  1. Go to https://reg.mpassociates.com/reglive/locateorder.aspx?confid=200, enter your email account and confirmation number and click on "Locate Order". This will direct you to the registration page.
  2. Open the "Colocated Conferences" tab, select the IWLS option, and click on "Checkout" to proceed to checkout.
For any question regarding the registration process, please email Register@dac.com or call the DAC offices at +1-303-530-4333.

Important Dates

It is mandatory to register a paper by submitting an abstract before the deadline below.

Paper abstract submission: March 18, 2016
Full paper submission: March 25, 2016 @ 11.59pm Anywhere on Earth
Notification of acceptance: April 15, 2016
Final version due: May 23, 2016

The submission deadline is final. There will be no extension.

Advanced Logic Synthesis Book

A book will be prepared to cover advances on Logic Synthesis presented at the conference in recent years. The book will be composed of different chapters. The authors of best papers presented at the conference will be invited to re-submit their work to be included in the book. Contributions on logic synthesis for novel technologies, different types of graph representations for logic synthesis, mixing logic synthesis and physical design, scalability of logic synthesis, and big data techniques applied to logic synthesis are especially welcome.

Submission instructions

Only complete papers with original and previously unpublished material are permitted. Submissions must be no longer than 8 pages, double column, 10-point font. Accepted papers are distributed only to IWLS participants.

EasyChair IWLS 2016 submission page

Resources for Students
Provided by the Technical Committee on VLSI (TCVLSI) from IEEE Computer Society

Best Student Paper Award: IWLS 2016 will be giving a Best Student Paper Award to a work of outstanding quality presented at the Workshop whose first author is a student. The award consists of US$ 150 and a certificate.
Student Travel Grants: IWLS 2016 will be giving two travel grants of US$ 250 for students.

To apply for a Student Travel Grant, complete the application form through the link:

Please, contact Andre Reis (andre dot reis at inf.ufrgs.br) if you have any question regarding student travel grants.

Organizing Committee

General Chair Rolf Drechsler University of Bremen/DFKI, Germany
Program Committee Chair André Reis UFRGS, Brazil
Special Sessions Co-Chair Jie-Hong Roland Jiang National Taiwan University, Taiwan
Special Sessions Co-Chair Robert Wille Johannes Kepler University Linz, Austria
Finance Chair Dirk Stroobandt Ghent University, Belgium
Publicity Chair Jody Maick Matos UFRGS, Brazil

Steering Committee

Dirk Stroobandt Ghent University, Belgium
Andre Reis UFRGS, Brazil
Ilya Wagner Intel, US
Valeria Bertacco University of Michigan, US
Philip Brisk University of California Riverside, US
Stephen A. Edwards Columbia University, US
Alan Mishchenko University of California Berkeley, US

Technical Program Committee

L. Amaru Synopsys, US V. Bertacco University of Michigan, US
P. Brisk University of California Riverside, US K.-H. Chang Avery Design Systems, US
R. Drechsler University of Bremen/DFKI, Germany E. Dubrova KTH, Sweden
S. A. Edwards Columbia University, US P. Ienne EPFL, Switzerland
N. Jayakumar Juniper Networks, US H.-R. Jiang National Chiao Tung University, ROC
J.-H. Jiang National Taiwan University, ROC T. Kam Intel, US
V. Kravets IBM T. J. Watson, US S. Krishnaswamy Columbia University, US
M. Martins Carnegie Mellon University, US A. Mishchenko U. of California Berkeley, US
S. Nowick Columbia University, US H. Parandeh Afshar Qualcomm, US
A. Pellegrini University of Michigan, US M. Purnaprajna Amrita University, India
W. Qian Shanghai Jiao Tong University, PRC R. Ribas UFRGS, Brazil
L. Rosa Jr. UFPel, Brazil K. Rupnow NTU and ADSC, Singapore
M. Soeken EPFL, Switzerland D. Stroobandt Ghent University, Belgium
C. Sze IBM Research, US T. Villa Università di Verona, Italy
I. Wagner Intel, US C.-Y. Wang National Tsing Hua University, ROC
T. Welp Yale University, US R. Wille Johannes Kepler University Linz, Austria


The IWLS community maintains a set of benchmarks, synthesized and mapped in Verilog and OpenAccess.

Links to Past Workshops

IWLS 2015: June 12 - June 13, 2015, Mountain View, California

IWLS 2014: May 30 - June 1, 2014, San Francisco, California

IWLS 2013: June 7 - June 8, 2013, Austin, Texas

IWLS 2012: June 1 - June 3, 2012, Berkeley, California

IWLS 2011: June 3 - June 5, 2011, San Diego, California

IWLS 2010: June 18 - June 20, 2010, Irvine, California

IWLS 2009: July 31 - August 2, 2009, Berkeley, California

IWLS 2008: June 4 - 6, 2008, Lake Tahoe, California

IWLS 2007: May 30 - June 1, 2007, San Diego, California

IWLS 2006: June 7 - 9, 2006, Vail, Colorado

IWLS 2005: June 8 - 10, 2005, Lake Arrowhead, California

IWLS 2004: June 2 - 4, 2004, Temecula Creek, California

IWLS 2003: May 28 - 30, 2003, Laguna Beach, California

IWLS 2002: June 4 - 7, 2002, New Orleans, Louisiana

IWLS 2001: June 12 - 15, 2001, Lake Tahoe, California

IWLS 2000: May 31 - June 2, 2000, Dana Point, California

Mailing List

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