2018

Co-located with the
Design Automation Conference

27th International Workshop
on Logic & Synthesis

June 23 – 24, 2018

Moscone Center West — San Francisco, CA

Moscone Center

Our sponsors

     
                

The International Workshop on Logic and Synthesis is the premier forum for research in synthesis, optimization, and verification of integrated circuits and systems. Research on logic synthesis for emerging technologies and for novel computing platforms, such as nanoscale systems and biological systems, is also strongly encouraged. The workshop encourages early dissemination of ideas and results. The workshop accepts complete papers highlighting important new problems in the early stages of development, without providing complete solutions. The emphasis is on novelty and intellectual rigor.

Topics of interest include, but are not limited to: hardware synthesis and optimization; software synthesis; hardware/software co-synthesis; power and timing analysis; testing, validation and verification; synthesis for reconfigurable architectures; hardware compilation for domain-specific languages; design experiences. Submissions on modeling, analysis and synthesis for emerging technologies and platforms are particularly encouraged.

The workshop format includes paper presentations, posters, invited talks, social lunch and dinner gatherings, and recreational activities. Accepted papers are distributed exclusively to IWLS participants.

Technical Program

The technical program consists of 16 regular talks, 2 posters and 3 keynotes.

Keynotes

The Circuit Complexity Project at NIST
Rene Peralta, NIST

Finding optimal circuits is computationally intractable under almost any meaningful metric. This is true even for linear circuits (i.e. those that use only XOR gates). Finding circuits with few nonlinear gates helps group linear gates into few connected components for minimization purposes. The minimum number of nonlinear gates needed to compute a function is called the "multiplicative complexity" of the function. I will discuss hardness results related to multiplicative complexity, circuit complexity, and linear circuit complexity. The Cryptographic Technologies Group at NIST has a project on circuit synthesis. We aim to i) identify metrics on combinational circuits that translate to area/delay/power on ASIC; ii) devise heuristics to optimize according to those metrics; iii) evaluate the resulting ASIC via simulation; iv) produce and evaluate a chip that implements various cryptographic functions. I will give a progress report on the project and describe some heuristics and results.

Rene Peralta is a computer scientist at NIST. He received a B.A. in Economics from Hamilton College in 1978. In 1980 Peralta received a M.S. in Mathematics from the State University of New York at Binghamton. In 1985 he received a Ph.D. in Computer Science from the University of California at Berkeley. For the next 20 years he held various positions in academia, mostly as a professor of cryptology, algorithmics and computational number theory. In 2005 he moved to NIST. He is currently with the Computer Security Division. Among the projects he is currently involved in are the Circuit Complexity Project (https://csrc.nist.gov/Projects/Circuit-Complexity), NIST Randomness Beacon Project (https://www.nist.gov/programs-projects/nist-randomness-beacon), Post Quantum Cryptography Project (https://csrc.nist.gov/projects/post-quantum-cryptography), and the Privacy Enhancing Cryptography Project (https://csrc.nist.gov/Projects/Privacy-Enhancing-Cryptography).

Looking Outside CMOS
Antun Domic, Synopsys

At its introduction in 1995, the Intel Pentium Pro was fabricated in a 500 nanometer BiCMOS process, it had 5.5 million transistors, it ran at 150 MHz with 30 watts of power consumption. Imagine a re-designed Pentium Pro fabricated in a 500nm RSFQ (Rapid Single Flux Quantum) process technology. Its clock rate could reach over 100 GHz, consuming a few watts as 99% of the SCE (Super Conducting Electronics) power consumption is in the cooling system. Around 1985, the TimberWolf Placement Software, done by Sechen and Sangiovanni-Vincentelli at UC Berkeley, could process a 2,700 cells circuit in 84 hours of CPU time on a DEC VAX 780 using 4 MB of memory, performing 75 million of annealing “moves”. If a simulated annealing placer could run on a 2,048 qubits quantum annealing machine, 1 billion cells could be placed, flat, in minutes, perhaps seconds. The computing and memory requirements of many applications, ranging from Artificial Intelligence (AI) to Biology greatly exceed the capabilities of current electronics. These needs are unlikely to be met by isolated improvements in transistors, data storage technologies or integrated circuit architectures. Over the last 25 years, EDA has been key in enabling the scaling of CMOS process technology. However, the ROI of moving to 5/3 nanometers is progressively smaller for most applications. Perhaps it is time to think outside the CMOS box. Josephson Junction-based SCE promises to invigorate High-Performance Computing by delivering over 10X more performance using 100X less power. So far it is the foundation for a new class of computers, based on the laws of quantum physics. Quantum Computing (QC) may change dramatically the landscape of imaging, pharmacology, finance, meteorology and, of course, security. Discrete and monolithic 3D may help unleashing the full potential of heterogeneous integration of different functions – compute, store, sense/actuate – each designed, implemented, and fabricated using the best available technology solution staying inside the general CMOS type technologies. This talk will offer an overview of some innovations that may dramatically change the landscape of the computer industry.

Antun is Synopsys’ Chief Technology Officer. As the company technical spokesperson, he focuses on aligning our advanced silicon roadmaps, driving our performance/low-power differentiation, and optimizing engineering execution across all business units. He previously served as Executive Vice President and General Manager of the Synopsys Design Group, for which he led the development of the company implementation and analog/mixed-signal product lines. Prior to joining Synopsys in 1997, Antun worked at Cadence Design Systems; at the Microprocessor Group of Digital Equipment Corporation in Hudson, Mass.; and at the Massachusetts Institute of Technology (MIT) Lincoln Laboratories in Lexington, Mass. Antun holds a BS from the University of Chile in Santiago and a PhD in Mathematics from MIT.

MemComputing with self-organizing logic gates
Massimiliano Di Ventra, UCSD

I will discuss how to employ memory (time non-locality) in a novel physics-based approach to computation, memcomputing, and its practical realization with self-organizing logic gates (SOLGs). SOLGs are terminal-agnostic gates that self-organize to always satisfy their logical proposition regardless to which terminal(s) the truth value is assigned. As examples, I will show the polynomial-time solution of prime factorization, the search version of the subset-sum problem, and approximations to the Max-SAT beyond the inapproximability gap using polynomial resources. I will also show that these digital memcomputing machines compute via an instantonic phase, implying that they are robust against noise and disorder. The digital memcomputing machines we propose can be efficiently simulated, are scalable and can be easily realized with available nanotechnology components.

Massimiliano Di Ventra obtained his undergraduate degree in Physics summa cum laude from the University of Trieste (Italy) in 1991 and did his PhD studies at the Ecole Polytechnique Federale de Lausanne (Switzerland) in 1993-1997. He has been Visiting Scientist at IBM T.J. Watson Research Center and Research Assistant Professor at Vanderbilt University before joining the Physics Department of Virginia Tech in 2000 as Assistant Professor. He was promoted to Associate Professor in 2003 and moved to the Physics Department of the University of California, San Diego, in 2004 where he was promoted to Full Professor in 2006. Di Ventra's research interests are in the theory of electronic and transport properties of nanoscale systems, non-equilibrium statistical mechanics, DNA sequencing/polymer dynamics in nanopores, and memory effects in nanostructures for applications in unconventional computing and biophysics. He has been invited to deliver more than 270 talks worldwide on these topics (including 12 plenary/keynote presentations, 9 talks at the March Meeting of the American Physical Society, 5 at the Materials Research Society, 2 at the American Chemical Society, and 2 at the SPIE). He has published more than 200 papers in refereed journals, co-edited the textbook Introduction to Nanoscale Science and Technology (Springer, 2004) for undergraduate students, he is single author of the graduate-level textbook Electrical Transport in Nanoscale Systems (Cambridge University Press, 2008), and of the book The Scientific Method: Reflections from a Practitioner (Oxford University Press, August 2018).



Registration

    Until May 30   From May 31
ACM/IEEE members:   Students   $200   $300
  Others   $350   $450
 
Non ACM/IEEE members:   Students   $300   $400
  Others   $500   $650

The cost of registration includes breakfasts, lunches, social event and coffee break service.

Register for IWLS on the DAC registration page following the instructions below:

If you are not registered at DAC:

  1. Go to https://reg.mpassociates.com/reglive/PromoCode.aspx?confid=251 and click on "Register". This will direct you to the registration page.
  2. Complete all the contact information and enter your membership status. Click "Select Your Participation". This will bring you to the product choice page.
  3. Open the "Colocated Conferences" tab, select the IWLS option, and click on "Checkout" to proceed to checkout.

If you are registered at DAC and would like to add an IWLS registration:

  1. Go to https://reg.mpassociates.com/reglive/locateorder.aspx?confid=251, enter your email account and confirmation number and click on "Locate Order". This will direct you to the registration page.
  2. Open the "Colocated Conferences" tab, select the IWLS option, and click on "Checkout" to proceed to checkout.
For any question regarding the registration process, please email Register@dac.com or call the DAC offices at +1-303-530-4333.

Important Dates

It is mandatory to register a paper by submitting an abstract before the deadline below.

Paper abstract submission: March 4, 2018
Full paper submission: March 11, 2018 @ 11.59pm Anywhere on Earth
Notification of acceptance: April 15, 2018
Final version due: May 13, 2018

The submission deadline is final. There will be no extension.

Submission instructions

Only complete papers with original and previously unpublished material are permitted. Submissions must be no longer than 8 pages, double column, 10-point font. Accepted papers are distributed only to IWLS participants.

EasyChair IWLS 2018 submission page

IWLS 2018 Programming Contest: "All the Best!"

In 2018, the IWLS organizing committee set up a programming contest. To participate, please follow these steps:

  1. Read the contest description.

  2. Write a computer program that takes as input a truth table in hexadecimal representation, a number of fanins k, and a number of gates r, that generates a BLN file as explained in the contest description. For example to synthesize the majority-of-three function as 4-gate circuits with 2-input gates, the program is called: "program 8e 2 4".

  3. We will publish the contest benchmark functions on April 27, 2018. These will be used to evaluate your algorithms.

  4. You need to submit your binary or source code and the resulting BLN files for the contest benchmarks until May 4, 2018. Please send everything via email to Mathias Soeken. We must be able to reproduce your results on our machines within a timeout of 60 minutes.

  5. We will submit the generated BLN files from your submissions until May 11, 2018 and announce all the results on this webpage.

  6. The submissions are rated according to the number of found solutions within the runtime limit of one hour. If for some benchmark a wrong solution is reported (i.e., it computes the wrong function or it does not respect the normalization rules), the overall count for that benchmark is halved for each wrong solution. (Example: If 3 wrong solutions are found, only 12.5% of the overall count will be considered in the final evaluation.)

  7. You are encouraged to share your source code with the IWLS community, but it's not required or has any effect on the rating. If you want to share, you can either point us to an online repository that we will link to this and the IWLS webpage. If you prefer to share the source code only among the IWLS participants, we will copy your code onto the proceeding pen drives.

Resources for Students
Provided by the Technical Committee on VLSI (TCVLSI) from IEEE Computer Society

Best Student Paper Award: IWLS 2018 will be giving a Best Student Paper Award to a work of outstanding quality presented at the Workshop whose first author is a student. The award consists of US$ 150 and a certificate.
Student Travel Grants: IWLS 2018 will be giving travel grants of US$ 250 for students. If you are interest, please send a mail including a brief proposal statement to robert.wille@jku.at. Deadline for applications is June 15, 2018.
Organizing Committee

General Chair Robert Wille Johannes Kepler University Linz, Austria
Program Committee Chair Jie-Hong Roland Jiang National Taiwan University, Taiwan
Special Session & Contest Chair Mathias Soeken EPFL, Switzerland
Finance Chair Pierre-Emmanuel Gaillardon University of Utah, USA
Publicity Chair Luca Amaru Synopsys, USA
Local Chair Vinicius Callegaro Mentor Graphics, USA

Steering Committee

Jie-Hong Roland Jiang National Taiwan University, Taiwan
Rolf Drechsler University of Bremen/DFKI GmbH, Germany
Andre Reis UFRGS, Brazil
Dirk Stroobandt Ghent University, Belgium
Alan Mishchenko University of California Berkeley, US

Technical Program Committee

L. Amaru Synopsys, USA V. Callegaro Mentor Graphics, USA
K.-H. Chang Avery Design Systems, USA M. Choudhury IBM T. J. Watson, USA
E. Dubrova KTH, Sweden R. Drechsler University of Bremen, Germany
S. A. Edwards Columbia University, USA M. Fujita University of Tokyo, Japan
P.-E. Gaillardon University of Utah, USA B. Ghavami Shahid Bahonar U. of Kerman, Iran
P. Ienne EPFL, Switzerland I.H.-R. Jiang National Taiwan University, Taiwan
J.-H.R. Jiang National Taiwan University, Taiwan V. Kravets IBM T. J. Watson, USA
F. Marranghello KTH, Sweden M. Martins Carnegie Mellon University, USA
J. Matos Silvaco, USA A. Mishchenko UC Berkeley, USA
A. Neutzling Cadence, UK M. Purnaprajna Amrita University, India
W. Qian Shanghai Jiao Tong U., China A. Reis UFRGS, Brazil
T. Sasao Meiji University, Japan M. Soeken EPFL, Switzerland
D. Stroobandt Ghent University, Belgium T. Villa Universita di Verona, Italy
R. Wille Johannes Kepler U., Austria C. Yu EPFL, Switzerland
Z. Zhang Cornell University, USA S. Das Xilinx Inc., USA

Benchmarks

The IWLS community maintains a set of logic synthesis benchmarks (IWLS'05 and EPFL), available in various formats.

Links to Past Workshops

IWLS 2017: June 17 - June 18, 2017, Austin, Texas

IWLS 2016: June 10 - June 11, 2016, Austin, Texas

IWLS 2015: June 12 - June 13, 2015, Mountain View, California

IWLS 2014: May 30 - June 1, 2014, San Francisco, California

IWLS 2013: June 7 - June 8, 2013, Austin, Texas

IWLS 2012: June 1 - June 3, 2012, Berkeley, California

IWLS 2011: June 3 - June 5, 2011, San Diego, California

IWLS 2010: June 18 - June 20, 2010, Irvine, California

IWLS 2009: July 31 - August 2, 2009, Berkeley, California

IWLS 2008: June 4 - 6, 2008, Lake Tahoe, California

IWLS 2007: May 30 - June 1, 2007, San Diego, California

IWLS 2006: June 7 - 9, 2006, Vail, Colorado

IWLS 2005: June 8 - 10, 2005, Lake Arrowhead, California

IWLS 2004: June 2 - 4, 2004, Temecula Creek, California

IWLS 2003: May 28 - 30, 2003, Laguna Beach, California

IWLS 2002: June 4 - 7, 2002, New Orleans, Louisiana

IWLS 2001: June 12 - 15, 2001, Lake Tahoe, California

IWLS 2000: May 31 - June 2, 2000, Dana Point, California

Mailing List

Subscribe to the IWLS mailing list. (The list is hidden and only its administrator can post to it.)

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