IWLS 2023

The International Workshop on Logic and Synthesis is the premier forum for research in synthesis, optimization, and verification of integrated circuits and systems. Research on logic synthesis for emerging technologies and for novel computing platforms, such as nanoscale systems and biological systems, is also strongly encouraged. The workshop encourages early dissemination of ideas and results. The workshop accepts complete papers highlighting important new problems in the early stages of development, without providing complete solutions. The emphasis is on novelty and intellectual rigor.

Topics of interest include, but are not limited to: hardware synthesis and optimization; software synthesis; hardware/software co-synthesis; power and timing analysis; testing, validation and verification; synthesis for reconfigurable architectures; hardware compilation for domain-specific languages; design experiences. Submissions on modeling, analysis, and synthesis for emerging technologies and platforms are particularly encouraged.

The workshop format includes paper presentations, posters, invited talks, social gatherings, and recreational activities. Accepted papers are distributed exclusively to IWLS participants.

Check out our call for papers.

Paper abstract submission:		April 3, 2023
Full paper submission:		April 10, 2023
Notification of acceptance:		May 15, 2023
Final version due:		June 02, 2023

Only complete papers with original and previously unpublished material are permitted. Submissions must be no longer than 8 pages, double column, 10-point font. Accepted papers are distributed only to IWLS participants.

It has been recently observed that the cost of silicon wafers has started to grow steeply in the 3rd quarter of 2021. Please note the hockey stick shape of the second graph here https://morethanmoore.substack.com/p/tsmc-financial-year-2022 As a result, the design area contributes more to the design cost, and there is increasing interest in high-effort area optimization methods, which is the topic of this year’s IWLS Programming Contest.

General Chair	Cunxi Yu	University of Utah, USA
Program Committee Chairs	Xiaoqing Xu/Lana Josipovic	Google X, USA/ETH Zurich, Switzerland
Program Contest Chair	Alan Mishchenko, Yukio Miyasaka	University of California Berkeley, USA
Special Session Chair	Eleonora Testa	Synopsys, USA
Finance Chair	Zhufei Chu	Ningbo University, China
Proceedings Chair	Walter Lau Neto	University of Utah/Synopsys, USA
Publicity Chairs	Augusto Neutzling/Yingjie Li	Cadence, UK/University of Utah, USA
Local Arrangements Chair	Siang-Yun Lee	EPFL, Switzerland

Luca Amaru		Synopsys, USA
Anna Bernasconi		Università di Pisa, Italy
Vinicius Callegaro		Siemens EDA, USA
Sat Chatterjee		Google, USA
Zhufei Chu		Ningbo University, China
Valentina Ciriani		Università degli Studi di Milano, Italy
Stephan Eggersglüß		Siemens EDA, Germany
Petr Fišer		CTU, Czech Republic
Jie-Hong Roland Jiang		National Taiwan University, Taiwan
Lana Josipović		ETH Zurich, Switzerland
Victor Kravets		IBM, USA
Siang-Yun Lee		EPFL, Switzerland
Yingjie Li		University of Utah, USA
Walter Lau Neto		University of Utah, USA
Giulia Meuli		Synopsys, Italy
Alan Mishchenko		UC Berkeley, USA
Augusto Neutzling		Cadence Design System, UK
Weikang Qian		Shanghai Jiao Tong University, China
Andre Reis		UFRGS, Brazil
Heinz Riener		Cadence Design System, Germany
Tsutomu Sasao		Meiji University, Japan
Herman Schmit		Google, USA
Mathias Soeken		Microsoft, USA
Eleonora Testa		Synopsys, USA
Tiziano Villa		Università degli Studi di Verona, Italy
Robert Wille		Johannes Kepler University, Austria
Xiaoqing Xu		X, the moonshot factory, USA
Cunxi Yu		University of Utah, USA

The IWLS community maintains a set of logic synthesis benchmarks (IWLS'05 and EPFL), available in various formats.

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