32nd International Workshop
on Logic & Synthesis

June 5 – 6, 2023

EPFL, Lausanne, Switzerland

Our sponsors


The International Workshop on Logic and Synthesis is the premier forum for research in synthesis, optimization, and verification of integrated circuits and systems. Research on logic synthesis for emerging technologies and for novel computing platforms, such as nanoscale systems and biological systems, is also strongly encouraged. The workshop encourages early dissemination of ideas and results. The workshop accepts complete papers highlighting important new problems in the early stages of development, without providing complete solutions. The emphasis is on novelty and intellectual rigor.

Topics of interest include, but are not limited to: hardware synthesis and optimization; software synthesis; hardware/software co-synthesis; power and timing analysis; testing, validation and verification; synthesis for reconfigurable architectures; hardware compilation for domain-specific languages; design experiences. Submissions on modeling, analysis, and synthesis for emerging technologies and platforms are particularly encouraged.

The workshop format includes paper presentations, posters, invited talks, social gatherings, and recreational activities. Accepted papers are distributed exclusively to IWLS participants.

Check out our call for papers.

Important Dates

EasyChair IWLS 2023 paper submission.

Paper abstract submission: April 3, 2023
Full paper submission: April 10, 2023
Notification of acceptance: May 15, 2023
Final version due: June 02, 2023

Submission Instructions

Only complete papers with original and previously unpublished material are permitted. Submissions must be no longer than 8 pages, double column, 10-point font. Accepted papers are distributed only to IWLS participants.

IWLS Programming Contest

IWLS 2023 Programming Contest Call for Contest

It has been recently observed that the cost of silicon wafers has started to grow steeply in the 3rd quarter of 2021. Please note the hockey stick shape of the second graph here https://morethanmoore.substack.com/p/tsmc-financial-year-2022 As a result, the design area contributes more to the design cost, and there is increasing interest in high-effort area optimization methods, which is the topic of this year’s IWLS Programming Contest.

IWLS 2023 Programming Contest Benchmarks

Submission instructions will be released soon.

Organizing Committee

General Chair Cunxi Yu University of Utah, USA
Program Committee Chairs Xiaoqing Xu/Lana Josipovic Google X, USA/ETH Zurich, Switzerland
Program Contest Chair Alan Mishchenko, Yukio Miyasaka University of California Berkeley, USA
Special Session Chair Eleonora Testa Synopsys, USA
Finance Chair Zhufei Chu Ningbo University, China
Proceedings Chair Walter Lau Neto University of Utah/Synopsys, USA
Publicity Chairs Augusto Neutzling/Yingjie Li Cadence, UK/University of Utah, USA
Local Arrangements Chair Siang-Yun Lee EPFL, Switzerland

Technical Program Committee (tentative)

Luca Amaru    Synopsys, USA
Anna Bernasconi    Università di Pisa, Italy
Vinicius Callegaro    Siemens EDA, USA
Sat Chatterjee    Google, USA
Zhufei Chu    Ningbo University, China
Valentina Ciriani    Università degli Studi di Milano, Italy
Stephan Eggersglüß    Siemens EDA, Germany
Petr Fišer    CTU, Czech Republic
Jie-Hong Roland Jiang    National Taiwan University, Taiwan
Lana Josipović    ETH Zurich, Switzerland
Victor Kravets    IBM, USA
Siang-Yun Lee    EPFL, Switzerland
Yingjie Li    University of Utah, USA
Walter Lau Neto    University of Utah, USA
Giulia Meuli    Synopsys, Italy
Alan Mishchenko    UC Berkeley, USA
Augusto Neutzling    Cadence Design System, UK
Weikang Qian    Shanghai Jiao Tong University, China
Andre Reis    UFRGS, Brazil
Heinz Riener    Cadence Design System, Germany
Tsutomu Sasao    Meiji University, Japan
Herman Schmit    Google, USA
Mathias Soeken    Microsoft, USA
Eleonora Testa    Synopsys, USA
Tiziano Villa    Università degli Studi di Verona, Italy
Robert Wille    Johannes Kepler University, Austria
Xiaoqing Xu    X, the moonshot factory, USA
Cunxi Yu    University of Utah, USA


The IWLS community maintains a set of logic synthesis benchmarks (IWLS'05 and EPFL), available in various formats.

Mailing List

Subscribe to the IWLS mailing list. (The list is hidden and only its administrator can post to it.)

Links to Past Workshops

IWLS 2022: July 18 - July 22, 2022, Virtual

IWLS 2021: July 19 - July 22, 2021, Virtual

IWLS 2020: July 27 - July 30, 2020, Virtual

IWLS 2019: June 21 - June 23, 2019, San Francisco, California

IWLS 2018: June 23 - June 24, 2018, San Francisco, California

IWLS 2017: June 17 - June 18, 2017, Austin, Texas

IWLS 2016: June 10 - June 11, 2016, Austin, Texas

IWLS 2015: June 12 - June 13, 2015, Mountain View, California

IWLS 2014: May 30 - June 1, 2014, San Francisco, California

IWLS 2013: June 7 - June 8, 2013, Austin, Texas

IWLS 2012: June 1 - June 3, 2012, Berkeley, California

IWLS 2011: June 3 - June 5, 2011, San Diego, California

IWLS 2010: June 18 - June 20, 2010, Irvine, California

IWLS 2009: July 31 - August 2, 2009, Berkeley, California

IWLS 2008: June 4 - 6, 2008, Lake Tahoe, California

IWLS 2007: May 30 - June 1, 2007, San Diego, California

IWLS 2006: June 7 - 9, 2006, Vail, Colorado

IWLS 2005: June 8 - 10, 2005, Lake Arrowhead, California

IWLS 2004: June 2 - 4, 2004, Temecula Creek, California

IWLS 2003: May 28 - 30, 2003, Laguna Beach, California

IWLS 2002: June 4 - 7, 2002, New Orleans, Louisiana

IWLS 2001: June 12 - 15, 2001, Lake Tahoe, California

IWLS 2000: May 31 - June 2, 2000, Dana Point, California

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DATE: Design, Automation and Test in Europe

ASPDAC: Asia and South Pacific Design Automation Conference

DAC: Design Automation Conference

ISPD: International Symposium on Physical Design

ISLPED: International Symposium on Low Power Electronics and Design

IWBDA: International Symposium on Bio-Design Automation