2023

32nd International Workshop on Logic & Synthesis June 5 – 6, 2023 EPFL, Lausanne, Switzerland

Our sponsors

Full Technical Program

The program consists of 6 regular paper sessions, 1 poster session, 2 keynotes, and 2 special sessions.

WiFi Access

Option 1: eduroam

If you have an eduroam certificate installed from your home institution, you should be able to connect 'eduroam' network from the available WiFi networks on your device, and log in using your institutional credentials.

Option 2: freewifi-epfl (Visitor WiFi Access)

1. Locate the 'freewifi-epfl' network from the list of available WiFi networks on your device.
2. Select the network and open a web browser.
3. You will be redirected to a login page where you need to enter your cell phone number.
4. You can choose SMS or Call to get the WiFi access

Registration Deadlines for Author/Early Bird: May 31, 2023
Registration site

If you are interested, kindly select the option for the "Pre-workshop Social Event: Vineyard Walk" in the registration form. Find the details of this event provided below.

Design Automation for Quantum Computing: How to (Not) Re-invent the Wheel for an Emerging Technology Robert Wille, Technical University of Munich, Germany Quantum computers are one of the most promising new technologies which are currently investigated. With physical realizations already available to a broader audience and several potential applications on the horizon, this raises the question how to efficiently design corresponding quantum computing solutions. Can we re-use established methods from the design automation of classical systems? Or do we have to start from scratch for quantum computing? This talk aims to provide answers to these questions. We are trying to make the point that we do not have to re-invent the wheel---but that a 1:1 re-use of classical design methods also won’t do the trick. The corresponding discussions are exemplified using design automation solutions and software tools from the Munich Quantum Toolkit (MQT). For more details, please see https://www.cda.cit.tum.de/research/quantum/. Robert Wille is a Full and Distinguished Professor at the Technical University of Munich, Germany, and Chief Scientific Officer at the Software Competence Center Hagenberg, Austria. He received the Diploma and Dr.-Ing. degrees in Computer Science from the University of Bremen, Germany, in 2006 and 2009, respectively. Since then, he worked at the University of Bremen, the German Research Center for Artificial Intelligence (DFKI), the University of Applied Science of Bremen, the University of Potsdam, and the Technical University Dresden. From 2015 until 2022, he was Full Professor at the Johannes Kepler University Linz, Austria, until he moved to Munich. His research interests are in the design of circuits and systems for both conventional and emerging technologies. In these areas, he published more than 400 papers and served in editorial boards as well as program committees of numerous journals/conferences such as TCAD, ASP-DAC, DAC, DATE, and ICCAD. For his research, he was awarded, e.g., with Best Paper Awards, e.g., at TCAD and ICCAD, an ERC Consolidator Grant, a Distinguished and a Lighthouse Professor appointment, a Google Research Award, and more.

Advanced Logic Synthesis Techniques for High-Performance Industrial Circuit Design Patrick Vuillod, Synopsys, France As circuit designs continue to grow in complexity, advanced tools and techniques are necessary to achieve cutting-edge designs. Our keynote will cover the latest updates on logic synthesis techniques used in the industrial design process. We will demonstrate how these techniques can be utilized to achieve superior frequency, area, and power consumption results in high-performance designs. Additionally, we will discuss the crucial factor of runtime and scalability on large core machines of design implementation process. Improving logic synthesis for greater speed is essential in maintaining consistent design times, especially with the increasing size of designs. Patrick Vuillod is part of the Synopsys R&D center in Grenoble, France. He has been working on Synopsys Implementation tools for 25 years. He has been developing optimization flows of Fusion Compiler, Design Compiler and ICC2 compiler. He worked on a broad area of topics such as logic optimization, multi-threaded delay optimization, routing congestion estimation algorithms and physical optimization, allowing several patents and papers. Previously Patrick received a PhD from INP Grenoble with an exchange at Stanford University.

Important Dates

EasyChair IWLS 2023 paper submission.

Paper abstract submission:		April 3, 2023	April 10, 2023
Full paper submission:		April 10, 2023	April 17, 2023 @ 11:59 pm Anywhere on Earth
Notification of acceptance:		May 15, 2023
Final version due:		June 02, 2023

Awards:

• Best Student Paper Award: $1,000 USD

Only complete papers with original and previously unpublished material are permitted. Submissions must be no longer than 8 pages, double column, 10-point font. Accepted papers are distributed only to IWLS participants.

IWLS 2023 Programming Contest Call for Contest

It has been recently observed that the cost of silicon wafers has started to grow steeply in the 3rd quarter of 2021. Please note the hockey stick shape of the second graph here https://morethanmoore.substack.com/p/tsmc-financial-year-2022 As a result, the design area contributes more to the design cost, and there is increasing interest in high-effort area optimization methods, which is the topic of this year’s IWLS Programming Contest.

IWLS 2023 Programming Contest Benchmarks

Contest Submission Deadline: May 31, 2023 11:59 pm Anywhere on Earth

Each team is expected to prepare 10 min presentation on the methods they used. The top 3 teams will present in the technical program.

Awards:

• Winner of each track: $500 USD

Submission site open: IWLS 2023 Programming Contest Submission.

General Chair		Cunxi Yu		University of Utah, USA
Program Committee Chairs		Xiaoqing Xu/Lana Josipovic		Google X, USA/ETH Zurich, Switzerland
Program Contest Chair		Alan Mishchenko, Yukio Miyasaka		University of California Berkeley, USA
Special Session Chair		Eleonora Testa		Synopsys, USA
Finance Chair		Zhufei Chu		Ningbo University, China
Proceedings Chair		Walter Lau Neto		University of Utah/Synopsys, USA
Publicity Chairs		Augusto Neutzling/Yingjie Li		Cadence, UK/University of Utah, USA
Local Arrangements Chair		Siang-Yun Lee		EPFL, Switzerland

Anna Bernasconi		Dipartimento di Informatica, Universita' di Pisa, Italy
Vinicius Callegaro		Visa, USA
Zhufei Chu		Ningbo University, China
Valentina Ciriani		University of Milan, Italy
Petr Fišer		Czech Technical University in Prague, Czech Republic
Winston Haaswijk		Cadence Design Systems, UK
Jie-Hong Roland Jiang		National Taiwan University, Taiwan
Lana Josipović		ETH Zurich, Switzerland
Victor Kravets		IBM, USA
Walter Lau Neto		Synopsys, USA
Alan Mishchenko		UC Berkeley, USA
Augusto Neutzling		Cadence Design Systems, UK
Weikang Qian		Shanghai Jiao Tong University, China
Andre Reis		UFRGS, Brazil
Heinz Riener		Cadence Design Systems, Germany
Tsutomu Sasao		Meiji University, Japan
Herman Schmit		Google, USA
Mathias Soeken		Microsoft, USA
Eleonora Testa		Synopsys, USA
Tiziano Villa		Università di Verona, Italy
Robert Wille		Technical University of Munich & SCCH GmbH, Germany
Xiaoqing Xu		X, the moonshot factory, USA
Cunxi Yu		University of Utah, USA

The IWLS community maintains a set of logic synthesis benchmarks (IWLS'05 and EPFL), available in various formats.

Subscribe to the IWLS mailing list. (The list is hidden and only its administrator can post to it.)

We are organizing a walk/light hike on Sunday, June 4, the day before the workshop through the Lavaux vineyards. This event is unofficially organized and possible public transportation costs are not covered by the official registration fee. Nevertheless, for organizational purposes, please indicate your interest in the registration form.

• 11:00 - 11:18 Take the CGNboat from Lausanne-Ouchy toLutry(12.00 CHF)
• 11:34 - 12:30 Walk up to restaurant Terra Rossa (2.5 km, 250 m ascent)
• Alternative if someone doesn't catch the boat or doesn't want to walk: Take train S5 to Bossière (11:32 - 11:40), then 1 km walk to restaurant; or take train S4 to Pully, then bus 47 to Lutry, Croix/Lutry (12:00 - 12:23), then 120 m walk to restaurant
• 12:30 - 14:30 Lunch at restaurant Terra Rossa (menu)
• 14:30 - 16:30 Walk along the vineyard until Cully (5 km, 270 m descent) or further along the lake until Rivaz-St-Saphorin (5 km more, flat), depending on participants' speed and strength
• Return from Cully: 17:25 - 18:05 by boat (14.00 CHF)
• Return from Rivaz-St-Saphorin: 17:10 - 18:05 by boat (18.00 CHF)
• Alternative return trains if the boat is not caught: from Cully 16:18 - 16:30 (every hour) by train S3 or 16:50 - 17:00 (every hour) by train S4 (5.60 CHF); from Rivaz or 17:13 - 17:30 (every hour) by train S3 (7.40 CHF) Participants are welcome to join for only part of the event, e.g., coming directly to the restaurant, meeting later or leaving early at Cully. Several volunteers will attend the hike and can assist in local transportation.

Workshop venue

EPFL BC 420 (map)

Near-by hotels

1. SwissTech Hotel: Directly at the EPFL metro station
2. Starling Hotel: On the other side of campus, 10 minutes walk from metro

From airport to EPFL by public transportation

• From Geneva airport ("Genève-Aéroport") or Zurich airport ("Zürich Flughafen"), take trains to either "Renens VD" station or "Lausanne" station. You may choose the destination depending on which connection fits your flight schedule better. If both are equally good, choosing "Renens VD" shall make the following metro connection easier. Travel time by train is around 1 hour from Geneva and around 2.5 hours from Zurich.
• From "Renens VD" station, take metro m1 to "EPFL" station (direction "Lausanne-Flon", 7 minutes).
• From "Lausanne" station, take metro m2 to "Lausanne-Flon" station (direction "Croisettes", 1 minute), then take metro m1 to "EPFL" station (direction "Renens", 13 minutes).
• Search for connections and buy tickets on the SBB website. It works not only for trains but also for metros and buses, so you can put "Ecublens VD, EPFL" as the destination.
• Map of local transportation in Lausanne: The pinks lines are metros. "Lausanne Gare" and "Renens VD" are the mentioned train stations. EPFL is at the bottom-left corner of the metro line m1.
• EPFL Campus Map

IWLS 2022: July 18 - July 22, 2022, Virtual

IWLS 2021: July 19 - July 22, 2021, Virtual

IWLS 2020: July 27 - July 30, 2020, Virtual

IWLS 2019: June 21 - June 23, 2019, Lausanne, Switzerland

IWLS 2018: June 23 - June 24, 2018, San Francisco, California

IWLS 2017: June 17 - June 18, 2017, Austin, Texas

IWLS 2016: June 10 - June 11, 2016, Austin, Texas

IWLS 2015: June 12 - June 13, 2015, Mountain View, California

IWLS 2014: May 30 - June 1, 2014, San Francisco, California

IWLS 2013: June 7 - June 8, 2013, Austin, Texas

IWLS 2012: June 1 - June 3, 2012, Berkeley, California

IWLS 2011: June 3 - June 5, 2011, San Diego, California

IWLS 2010: June 18 - June 20, 2010, Irvine, California

IWLS 2009: July 31 - August 2, 2009, Berkeley, California

IWLS 2008: June 4 - 6, 2008, Lake Tahoe, California

IWLS 2007: May 30 - June 1, 2007, San Diego, California

IWLS 2006: June 7 - 9, 2006, Vail, Colorado

IWLS 2005: June 8 - 10, 2005, Lake Arrowhead, California

IWLS 2004: June 2 - 4, 2004, Temecula Creek, California

IWLS 2003: May 28 - 30, 2003, Laguna Beach, California

IWLS 2002: June 4 - 7, 2002, New Orleans, Louisiana

IWLS 2001: June 12 - 15, 2001, Lake Tahoe, California

IWLS 2000: May 31 - June 2, 2000, Dana Point, California

ICCAD: International Conference on Computer-Aided Design

DATE: Design, Automation and Test in Europe

ASPDAC: Asia and South Pacific Design Automation Conference

DAC: Design Automation Conference

ISPD: International Symposium on Physical Design

ISLPED: International Symposium on Low Power Electronics and Design

IWBDA: International Symposium on Bio-Design Automation