2024 |
33rd International Workshop on Logic & Synthesis June 6–7, 2024 ETH Zurich, Zurich, Switzerland
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Our sponsors
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| IWLS 2024 Technical Program |
Link to the workshop proceedings
| THURSDAY JUNE 6TH | ||
| 9:00–9:10: Welcome coffee | ||
| 9:10–9:20: Opening session | Opening Keynote: Lana Josipović & Winston Haaswijk | |
| 9:20–10:20: Keynote | Keynote 1 (Chair: Lana Josipović) | |
| Can AI Design and Verify Your Design? [Slides] | Ziyad Hanna (Cadence Design Systems) | |
| 10:20–11:00: Paper session | Session 1: Resubstitution Revisited (Chair: Siang-Yun Lee) | |
| 24 | Information Graph-Based Resubstitution For Networks of Look-Up Tables (best student paper 🏆) | Andrea Costamagna, Alessandro Tempia Calvino (EPFL), Alan Mishchenko (UC Berkeley), and Giovanni De Micheli (EPFL) |
| 25 | Post-Mapping Resubstitution For Area-Oriented Optimization | Andrea Costamagna, Alessandro Tempia Calvino (EPFL), Alan Mishchenko (UC Berkeley), and Giovanni De Micheli (EPFL) |
| 11:00–11:30: Coffee break | ||
| 11:30–12:50: Paper session | Session 2: New Flavours of Logic Synthesis (Chair: Stefan Nikolić) | |
| 6 | Randomized transduction for high-effort logic synthesis | Yukio Miyasaka, Alan Mishchenko, John Wawrzynek (UC Berkeley), Dino Ruic, and Xiaoqing Xu (X, the moonshot factory) |
| 7 | New Stories on the Structural Bias | Petr Fišer and Jan Schmidt (Czech Technical University in Prague) |
| 20 | Row-Shift Decompositions for Classification Functions: Application to Machine Learning Problems | Tsutomu Sasao (Meiji University) |
| 13 | Practical Boolean Decomposition for Delay-driven LUT Mapping (best student paper candidate) | Alessandro Tempia Calvino (EPFL), Alan Mishchenko (UC Berkeley), Giovanni De Micheli (EPFL), and Robert Brayton (UC Berkeley) |
| 12:50–14:30: Lunch | Lunch at Dozentenfoyer (in the ETH main building, on floor J / top floor) | |
| 14:30–15:10: Paper session | Session 3: Respecting Our Boundaries? (Chair: Dirk Stroobandt) | |
| 14 | Recovering Hierarchical Boundaries in a Flat Netlist (best student paper candidate) | Kuo-Wei Ho, Yu-Wei Fan, Jie-Hong Roland Jiang (National Taiwan University), Alan Mishchenko, Robert Brayton (UC Berkeley), and Sean Weaver (U.S. National Security Agency) |
| 17 | To Box or Not to Box: Preserving Special Logic Blocks in Technology-Independent Logic Optimization | Siang-Yun Lee and Heinz Riener (Cadence Design Systems) |
| 15:10–15:30: Poster session | Poster Session (Chair: Dirk Stroobandt) | |
| 3 | Maelstrom: A Logic Synthesis Technique for Asynchronous Circuits | Karthi Srinivasan and Rajit Manohar (Yale University) |
| 16 | Logic Synthesis with Generative Deep Neural Networks | Xihan Li (University College London), Xing Li, Lei Chen, Xing Zhang, Mingxuan Yuan (Huawei Noah's Ark Lab), and Jun Wang (University College London) |
| 9 | A Systematic Framework for Opportunistic Pruning of Deep Neural Networks on Edge Devices | Robert Viramontes and Azadeh Davoodi (University of Wisconsin–Madison) |
| 15:30–16:00: Poster & coffee | ||
| 16:00–17:00: Special session | Special Session: Unconventional Cost Functions for Logic Synthesis (Chair: Petr Fišer) | |
| Logic Synthesis for Emerging Nanocircuits | Zhufei Chu (Ningbo University) | |
| The Case for Planar Logic Synthesis: Crossing Costs in Nanotech [Slides] | Marcel Walter (Technical University of Munich) | |
| 17:00–17:30: Contest session | Programming Contest Award | |
| Dinner at Johanniter (Niederdorfstrasse 70, 8001 Zürich) We meet up at the restaurant between 19:00–19:30; the dinner starts at 19:30 |
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| FRIDAY JUNE 7TH | ||
| 9:00–9:10: Welcome coffee | ||
| 9:10–10:10: Keynote | Keynote 2 (Chair: Winston Haaswijk) | |
| Symmetric Is Better: Can We Exploit Regularities in Logic Synthesis? [Slides] | Valentina Ciriani (University of Milano) | |
| 10:10–10:50: Paper session | Session 4: Verfication (Chair: Heinz Riener) | |
| 10 | SimGen: Simulation Pattern Generation for Efficient Equivalence Checking | Carmine Rizzi, Sarah Brunner (ETH Zurich), Alan Mishchenko (UC Berkeley), and Lana Josipović (ETH Zurich) |
| 29 | Elevating Boolean Matching to the Word Level (best student paper candidate) | Jiun-Hao Chen, Hsin-Ying Tsai, Kuo-Wei Ho, and Jie-Hong Roland Jiang (National Taiwan University) |
| 10:50–11:20: Coffee break | ||
| 11:20–12:40: Paper session | Session 5: More Logic Synthesis! (Chair: Alan Mishchenko) | |
| 5 | Reducing Wire Crossings in Field-Coupled Nanotechnologies | Benjamin Hien, Marcel Walter (Technical University of Munich), and Robert Wille (Technical University of Munich, Software Competence Center Hagenberg GmbH) |
| 11 | Insights from Basilisk: Are Open-Source EDA Tools Ready for a Multi-Million-Gate, Linux-Booting RV64 SoC Design? | Philippe Sauter, Thomas Benz, Paul Scheffler, Frank K. Gürkaynak (ETH Zurich), and Luca Benini (ETH Zurich, University of Bologna) |
| 12 | Enabling Scalable Sequential Synthesis and Formal Verification in an Industrial Flow | Eleonora Testa (Synopsys), Dewmini Marakkalage (EPFL), Michael Quayle, Sudipta Kundu, Abhishek Kumar, Diptanshu Ghosh, Giulia Meuli (Synopsys), Giovanni De Micheli (EPFL), and Luca Amaru (Synopsys) |
| 21 | CRUSH: A Credit-Based Approach for Functional Unit Sharing in Dynamically Scheduled HLS | Jiahui Xu and Lana Josipović (ETH Zurich) |
| 12:40–12:55: Benchmark session | EPFL Benchmark Results Update | Alessandro Tempia Calvino (EPFL) |
| 12:55–14:40: Lunch | Lunch at Dozentenfoyer (in the ETH main building, on floor J / top floor) | |
| 14:40–15:40: Keynote | Keynote 3 (Chair: Giovanni De Micheli) | |
| Toward Software-to-Atoms Open-Source RISC-V Computing Platforms: Is Open-Source Synthesis Ready for Prime Time? [Slides] | Luca Benini (ETH Zurich, University of Bologna) | |
| 15:40–16:00: Coffee break | ||
| 16:00–17:20: Paper session | Session 6: Machine Learning for Synthesis (Chair: Marcel Walter) | |
| 22 | Global Crossover: An Evolution Strategy for Logic Synthesis | Hanyu Wang (ETH Zurich), Chang Meng, and Giovanni De Micheli (EPFL) |
| 8 | On Neural Networks for Automatic Test Pattern Generation | Lizi Zhang and Azadeh Davoodi (University of Wisconsin–Madison) |
| 27 | HardCore Generation: Generating Hard UNSAT Problems for Data Augmentation | Joseph Cotnareanu (McGill University), Zhanguang Zhang, Hui-Ling Zhen, Yingxue Zhang (Huawei Noah's Ark Lab), and Mark Coates (McGill University) |
| 26 | GraSS: Combining Graph Neural Networks with Expert Knowledge for SAT Solver Selection | Zhanguang Zhang, Didier Chetelat (Huawei Noah's Ark Lab), Joseph Cotnareanu (McGill University), Amur Ghose, Wenyi Xiao, Hui-Ling Zhen, Yingxue Zhang, Jianye Hao (Huawei Noah's Ark Lab), Mark Coates (McGill University), and Mingxuan Yuan (Huawei Noah's Ark Lab) |
| 17:20–17:30: Closing session | Closing Session & Best Paper Award | |
| SATURDAY JUNE 8TH | ||
| We are organizing a walk/light hike at Uetliberg mountain on Saturday, June 8th (the day after the workshop). This event is unofficially organized and the official registration fee does not cover public transportation costs. Nevertheless, please indicate your interest in the registration form for organizational purposes. The event will start at 10 am and end at approximately 6 pm; yet, there is a possibility to join later or leave early (see detailed schedule here). | ||