|
2026
|
|
35th International Workshop
on Logic & Synthesis
May 29–31, 2026
Hong Kong, China
|
Our sponsors
The International Workshop on Logic and Synthesis is the premier forum for research in synthesis, optimization, and verification of integrated circuits and systems. Research on logic synthesis for emerging technologies and for novel computing platforms, such as nanoscale systems and biological systems, is also strongly encouraged. The workshop encourages the early dissemination of ideas and results. The workshop accepts complete papers highlighting important new problems in the early stages of development, without providing complete solutions. The emphasis is on novelty and intellectual rigor.
Topics of interest include but are not limited to: hardware synthesis and optimization; software synthesis; hardware/software co-synthesis; power and timing analysis; testing, validation, and verification; synthesis for reconfigurable architectures; hardware compilation for domain-specific languages; and design experiences. Submissions on modeling, analysis, and synthesis for emerging technologies and platforms are particularly encouraged.
The workshop format includes paper presentations, invited talks, social lunch and dinner
gatherings, and recreational activities.
Check out our call for papers.
| IWLS 2026 Technical Program |
Full Technical Program
The program consists of 8 regular paper sessions, 1 poster session, 2 keynotes.
| Registration Is Open Now! |
Early registration deadline: May 20, 2026
Registration site
| Registration Category |
Early Registration (On or before May 20) |
Late Registration (After May 20) |
| Student |
$300 |
$400 |
| IEEE/ACM Member |
$400 |
$500 |
| Non-IEEE/ACM Member |
$500 |
$600 |
| IEEE/ACM Life Member |
$220 |
$300 |
If needed, the VISA request information and instruction will be shown during the registration process.
| Paper abstract submission: |
|
March 20, 2026 (AoE) March 27, 2026 (AoE) |
| Full paper submission: |
|
March 27, 2026 (AoE) April 3, 2026 (AoE) |
| Notification of acceptance: |
|
May 3, 2026 (AoE) May 8, 2026 (AoE) |
| Final version due: |
|
May 20, 2026 (AoE) |
Only complete papers with original and previously unpublished
material are permitted. Submissions must be no longer than 8 pages (references excluded),
double column, 10-point font (we recommend using
the ACM template
or the IEEE template,
but not necessarily). Accepted papers are distributed only to
IWLS participants.
Double-blind policy: IWLS uses a double-blind reviewing system.
Manuscripts must not identify authors or their affiliations; those
that do will not be considered.
If you have questions about how to meet these guidelines, please contact the
program chairs before the submission deadline.
EasyChair IWLS 2026 submission page
The IWLS Programming Contest this year continues the logic-synthesis competitions held at IWLS in recent years. In contrast to previous years, the objective of this contest is
not to find a single “best” solution per benchmark. Instead, the goal is to explore the
tradeoff between area and delay.
For details, please check out the call for submission for the programming contest below.
IWLS 2026 Programming Contest Call for Submissions
Benchmarks. 100 new practical benchmarks, with file names ex200.truth through
ex299.truth, were generated for this contest (with possibly a few duplicates from the
previous years). The high-level descriptions are not disclosed because this is a logic
synthesis competition and the participants are encouraged to develop optimization
methods that are universally applicable, rather than tailored to specific known circuits.
IWLS 2026 Programming Contest Benchmarks
Submission deadline: May 22, 2026 (AoE)
Submission site: IWLS 2026 Contest Submission
|
AI-Hardware Co-Design: Advancing Quality, Productivity, and Reliability
Deming Chen,
University of Illinois at Urbana-Champaign, USA
Abstract: AI workloads, from edge intelligence to large language models (LLMs), are placing
unprecedented demands on computing systems, exposing fundamental challenges in efficiency,
productivity, and reliability, making AI-hardware (AI-HW) co-design essential. This talk presents
a unified view of AI-HW co-design across models, synthesis, architectures, and systems,
demonstrating how coupling AI algorithms with hardware specialization reshapes performance,
energy efficiency, and system robustness. It highlights the A3C3 (AI Algorithm-Accelerator Co-
design, Co-search, and Co-generation) methodology, realized through FPGA- and GPU-based
systems such as SkyNet, a co-designed model that won double championships at DAC 2019,
and extends these principles to LLMs through works like Medusa, SnapKV, and StreamTensor
for improved latency and energy efficiency. It further explores reliability through Proof2Silicon,
integrating LLMs, formal verification, and hardware synthesis to bridge natural language
specifications and silicon implementations. Together, these efforts illustrate how end-to-end
AI-HW co-design provides a scalable framework for advancing quality, productivity, and
reliability in next-generation AI systems.
Speaker bio: Deming Chen is the Abel Bliss Professor in the Grainger College of Engineering at the
University of Illinois Urbana-Champaign. His research interests include machine learning and
AI, system-level design methodologies, hybrid cloud systems, security and confidential
computing, and reconfigurable and heterogeneous computing. He has published more than 300
research papers, received 10 Best Paper Awards, 2 ACM/SIGDA TCFPGA Hall-of-Fame Paper
Awards, 5 Best Poster Awards, and delivered more than 170 invited talks, including over 20
keynote and distinguished lectures. His research has generated substantial impact, with several
open-source solutions adopted by industry (e.g., FCUDA, DNNBuilder, CSRNet, SkyNet,
ScaleHLS, Medusa). Dr. Chen is an ACM Fellow, an IEEE Fellow, and previously served as
Editor-in-Chief of ACM Transactions on Reconfigurable Technology and Systems (TRETS).
Under his leadership, the impact factor of ACM TRETS has increased by 3.8 times. He serves
as the Illinois Director of the IBM-Illinois Discovery Accelerator Institute and the Director of the
AMD Center of Excellence. Additionally, he has been involved in several startup companies,
including AutoESL and Inspirit IoT. He received his Ph.D. in Computer Science from UCLA in
2005.
|
|
Logic Synthesis at Scale and Speed
Evangeline F.Y. Young,
The Chinese University of Hong Kong, China
Abstract: Logic synthesis has traditionally been shaped by CPU centric algorithms,
where limited parallelism constrains both scalability and turnaround time
as designs continue to grow in size and complexity. At the same time,
modern computing platforms now offer unprecedented levels of massive
parallelism in the form of GPUs and many cores CPU, challenging long
standing assumptions about how synthesis algorithms should be designed and
implemented.
The keynote outlines a vision for logic synthesis, where algorithms are
co-designed with heterogeneous hardware in mind, enabling orders of
magnitude speedups. We explore how core logic synthesis tasks can be
fundamentally restructured for parallel paradigm. Drawing on recent
research and experience, the talk highlights both the opportunities and
challenges of acceleration for logic synthesis, including performance,
scalability, and integration into existing EDA flows.
Speaker bio: Evangeline Young received her B.Sc. and M.Phil. degree in Computer Science from The
Chinese University of Hong Kong and received her Ph.D. degree from The University of Texas
at Austin. BTW, she accepted Jesus on Oct 20, 1996. She joined the Department of Computer
Science and Engineering in the Chinese University of Hong Kong as an assistant professor and
is now a professor in the same department. Her research interests include CAD of VLSI circuits,
algorithms, combinatorial optimization and AI. She has served in the program committees of
DAC, ICCAD, ASP-DAC, ISPD, GLSVLSI, DATE and the editorial boards of IEEE TCAD, ACM
TODAES and Integration, the VLSI Journal. She also served in the executive committee of
ISPD and ICCAD. Her research group has won championships and prizes in renown EDA
contests, including the 2018-20, 2015-16, 2012-13, CAD Contests at ICCAD, DAC 2012, and
ISPD 2015-20 and 2010-11.
|
Workshop venue
Recommended Nearby Hotels
| General Chair |
|
Zhufei Chu |
|
Ningbo University |
| Program Committee Chairs |
|
Walter Lau Neto Weikang Qian |
|
Synopsys Shanghai Jiao Tong University |
| Program Contest Chairs |
|
Alan Mishchenko Attila Jurecska |
|
UC Berkeley Siemens EDA |
| Special Session Chair |
|
Tsung-Yi Ho |
|
Chinese University of Hong Kong |
| Finance Chair |
|
Fengbin Tu |
|
The Hong Kong University of Science and Technology |
| Proceedings Chair |
|
Guojie Luo |
|
Peking University |
| Publicity Chairs |
|
Cunxi Yu Marcel Walter |
|
University of Maryland Technical University of Munich |
| Local Arrangements Chairs |
|
Rongliang Fu Zhenxuan Xie |
|
Chinese University of Hong Kong Chinese University of Hong Kong |
| Technical Program Committee |
| Luca Amarù | | Synopsys, USA |
| Anna Bernasconi | | University of Pisa, Italy |
| Lei Chen | | Huawei Noah’s Ark Lab, Hong Kong SAR |
| Zhufei Chu | | Ningbo University, China |
| Fabrizio Ferrandi | | Politecnico di Milano, Italy |
| Petr Fišer | | Czech Technical University in Prague, Czech Republic |
| Rongliang Fu | | The Chinese University of Hong Kong, China |
| Aman Gayasen | | AMD, USA |
| Winston Haaswijk | | Cadence Design Systems, USA |
| Jie-Hong Roland Jiang | | National Taiwan University, Taiwan |
| Attila Jurecska | | Siemens EDA, USA |
| Victor Kravets | | IBM, USA |
| Walter Lau Neto | | Synopsys, USA |
| Siang-Yun Lee | | Cadence Design Systems, USA |
| Guojie Luo | | Peking University, China |
| Chang Meng | | Eindhoven University of Technology, Netherlands |
| Giulia Meuli | | Synopsys, USA |
| Shin-ichi Minato | | Kyoto University, Japan |
| Alan Mishchenko | | University of California, Berkeley, USA |
| Augusto Neutzling | | Real Intent, USA |
| Stefan Nikolić | | University of Novi Sad, Serbia |
| Weikang Qian | | Shanghai Jiao Tong University, China |
| Stefano Quer | | Politecnico di Torino, Italy |
| Andre Reis | | UFRGS, Brazil |
| Tsutomu Sasao | | Meiji University, Japan |
| Herman Schmit | | Google, USA |
| Eleonora Testa | | Synopsys, USA |
| Alessandro Tempia Calvino | | Synopsys, USA |
| Gabriella Trucco | | University of Milan, Italy |
| Tiziano Villa | | University of Verona, Italy |
| Marcel Walter | | Technical University of Munich, Germany |
| Robert Wille | | Technical University of Munich & SCCH GmbH, Germany |
| Cunxi Yu | | University of Maryland, College Park, USA |
| Mingfei Yu | | EPFL, Switzerland |
The IWLS community maintains a set
of logic synthesis benchmarks (IWLS'05 and EPFL), available in various formats.
Subscribe
to the IWLS mailing list. (The list is hidden and only its
administrator can post to it.)
IWLS 2025: June 12 - June 13, 2025, Verona, Italy
IWLS 2024: June 6 - June 7, 2024, Zurich, Switzerland
IWLS 2023: June 5 - June 5, 2023, Lausanne, Switzerland
IWLS 2022: July 18 - July 22, 2022, Virtual
IWLS 2021: July 19 - July 22, 2021, Virtual
IWLS 2020: July 27 - July 30, 2020, Virtual
IWLS 2019: June 21 - June 23, 2019, Lausanne, Switzerland
IWLS 2018: June 23 - June 24, 2018, San Francisco, California
IWLS 2017: June 17 - June 18, 2017, Austin, Texas
IWLS 2016: June 10 - June 11, 2016, Austin, Texas
IWLS 2015: June 12 - June 13, 2015, Mountain View, California
IWLS 2014: May 30 - June 1, 2014, San Francisco, California
IWLS 2013: June 7 - June 8, 2013, Austin, Texas
IWLS 2012: June 1 - June 3, 2012, Berkeley, California
IWLS 2011: June 3 - June 5, 2011, San Diego, California
IWLS 2010: June 18 - June 20, 2010, Irvine, California
IWLS 2009: July 31 - August 2, 2009, Berkeley, California
IWLS 2008: June 4 - 6, 2008, Lake Tahoe, California
IWLS 2007: May 30 - June 1, 2007, San Diego, California
IWLS 2006: June 7 - 9, 2006, Vail, Colorado
IWLS 2005: June 8 - 10, 2005, Lake Arrowhead, California
IWLS 2004: June 2 - 4, 2004, Temecula Creek, California
IWLS 2003: May 28 - 30, 2003, Laguna Beach, California
IWLS 2002: June 4 - 7, 2002, New Orleans, Louisiana
IWLS 2001: June 12 - 15, 2001, Lake Tahoe, California
IWLS 2000: May 31 - June 2, 2000, Dana Point, California
ICCAD: International Conference on Computer-Aided Design
DATE: Design, Automation and Test in Europe
ASPDAC: Asia and South Pacific Design Automation Conference
DAC: Design Automation Conference
ISPD: International Symposium on Physical Design
ISLPED: International Symposium on Low Power Electronics and Design
IWBDA: International Symposium on Bio-Design Automation
|