2027

36th International Workshop on Logic & Synthesis May 17–19, 2027 Shanghai, China

Our sponsors

The International Workshop on Logic and Synthesis is the premier forum for research in synthesis, optimization, and verification of integrated circuits and systems. Research on logic synthesis for emerging technologies and for novel computing platforms, such as nanoscale systems and biological systems, is also strongly encouraged. The workshop encourages the early dissemination of ideas and results. The workshop accepts complete papers highlighting important new problems in the early stages of development, without providing complete solutions. The emphasis is on novelty and intellectual rigor.

Topics of interest include, but are not limited to, hardware synthesis and optimization; software synthesis; hardware/software co-synthesis; power and timing analysis; testing, validation, and verification; synthesis for reconfigurable architectures; hardware compilation for domain-specific languages; and design experiences. Submissions on modeling, analysis, and synthesis for emerging technologies and platforms are particularly encouraged.

The workshop format includes paper presentations, invited talks, social lunch and dinner gatherings, and recreational activities.

Check out our call for papers.

Full Technical Program

Registration information will be announced here.

Paper abstract submission:	February 8, 2027 (AoE) (same for special sessions)
Full paper submission:	February 15, 2027 (AoE)
Notification of acceptance:	March 21, 2027 (AoE)
Final version due:	May 8, 2027 (AoE)

The call for papers and submission instructions will be announced here.

The IWLS Programming Contest continues the logic-synthesis competitions held at IWLS in recent years. As in 2026, the objective is not to find a single best solution per benchmark. Instead, the goal is to explore the tradeoff between delay and area and to produce a high-quality Pareto curve for each benchmark.

The 2027 contest uses gate-level networks composed of AOI/OAI gates and a transistor-level cost model. Please consult the call for submissions for the complete contest rules.

Contest materials

• IWLS 2027 Programming Contest Call for Submissions (PDF)
• IWLS 2027 Programming Contest Benchmarks (ZIP) — the 100 practical benchmarks, from ex200.truth through ex299.truth, are reused from the 2026 contest.
• IWLS 2027 genlib library

Submission deadline and submission site will be announced here.

• Professor Giovanni De Micheli from EPFL
• Dr. Luca Amaru from Synopsys
• Dr. Yu Huang from Huawei

Workshop venue

The workshop will be held at the State Key Laboratory of Integrated Chips and Systems. Please check the travel information for more details.

State Key Laboratory of Integrated Chips and Systems

General Chair		Lingli Wang		Fudan University
Program Committee Chairs		Marcel Walter Hongce Zhang		Technical University of Munich Hong Kong University of Science and Technology (Guangzhou)
Program Contest Chairs		Alan Mishchenko Attila Jurecska Walter Lau Neto		UC Berkeley Siemens EDA Synopsys
Special Session Chairs		Shenggen Zheng Jianguo Yang Zhiang Wang		Quantum Science Center of Guangdong-Hong Kong-Macao Greater Bay Area Zhangjiang Laboratory Fudan University
Finance Chair		Zhufei Chu		Ningbo University
Proceedings Chair		Weikang Qian		Shanghai Jiao Tong University
Industry Chairs		Yu Huang Ankush Sood		Huawei Cadence
Publicity Chairs		Guojie Luo Xi Wang Shanshi Huang Letian Huang		Peking University Southeast University Hong Kong University of Science and Technology (Guangzhou) University of Electronic Science and Technology of China
Web Chairs		Keren Zhu Yaojia Wang		Fudan University Fudan University
Local Arrangements Chairs		Siting Liu Xinfei Guo You Li		ShanghaiTech University Shanghai Jiao Tong University Fudan University

General Chair		Lingli Wang		Fudan University
Program Committee Chairs		Marcel Walter		Technical University of Munich
		Hongce Zhang		Hong Kong University of Science and Technology (Guangzhou)
Program Contest Chairs		Alan Mishchenko		UC Berkeley
		Attila Jurecska		Siemens EDA
		Walter Lau Neto		Synopsys
Special Session Chairs		Shenggen Zheng		Quantum Science Center of Guangdong-Hong Kong-Macao Greater Bay Area
		Jianguo Yang		Zhangjiang Laboratory
		Zhiang Wang		Fudan University
Finance Chair		Zhufei Chu		Ningbo University
Proceedings Chair		Weikang Qian		Shanghai Jiao Tong University
Industry Chairs		Yu Huang		Huawei
		Ankush Sood		Cadence
Publicity Chairs		Guojie Luo		Peking University
		Xi Wang		Southeast University
		Shanshi Huang		Hong Kong University of Science and Technology (Guangzhou)
		Letian Huang		University of Electronic Science and Technology of China
Web Chairs		Keren Zhu		Fudan University
		Yaojia Wang		Fudan University
Local Arrangements Chairs		Siting Liu		ShanghaiTech University
		Xinfei Guo		Shanghai Jiao Tong University
		You Li		Fudan University

Luca Amarù		Synopsys
Anna Bernasconi		University of Pisa
Lei Chen		Huawei Noah’s Ark Lab
Zhufei Chu		Ningbo University
Fabrizio Ferrandi		Politecnico di Milano
Petr Fišer		Czech Technical University in Prague
Rongliang Fu		The Chinese University of Hong Kong
Aman Gayasen		AMD
Winston Haaswijk		Cadence Design Systems
Jie-Hong Roland Jiang		National Taiwan University
Attila Jurecska		Siemens EDA
Victor Kravets		IBM
Walter Lau Neto		Synopsys
Siang-Yun Lee		Cadence Design Systems
Guojie Luo		Peking University
Chang Meng		Eindhoven University of Technology
Giulia Meuli		Synopsys
Shin-ichi Minato		Kyoto University
Alan Mishchenko		University of California, Berkeley
Augusto Neutzling		Real Intent
Stefan Nikolić		University of Novi Sad
Weikang Qian		Shanghai Jiao Tong University
Stefano Quer		Politecnico di Torino
Andre Reis		UFRGS
Tsutomu Sasao		Meiji University
Herman Schmit		Google
Eleonora Testa		Synopsys
Alessandro Tempia Calvino		Synopsys
Gabriella Trucco		University of Milan
Tiziano Villa		University of Verona
Marcel Walter		Technical University of Munich
Robert Wille		Technical University of Munich & SCCH GmbH
Cunxi Yu		University of Maryland, College Park
Mingfei Yu		EPFL

The IWLS community maintains a set of logic synthesis benchmarks (IWLS'05 and EPFL), available in various formats.

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IWLS 2026: May 29–31, 2026, Hong Kong, China

IWLS 2025: June 12–13, 2025, Verona, Italy

IWLS 2024: June 6–7, 2024, Zurich, Switzerland

IWLS 2023: June 5, 2023, Lausanne, Switzerland

IWLS 2022: July 18–22, 2022, Virtual

IWLS 2021: July 19–22, 2021, Virtual

IWLS 2020: July 27–30, 2020, Virtual

IWLS 2019: June 21–23, 2019, Lausanne, Switzerland

IWLS 2018: June 23–24, 2018, San Francisco, California

IWLS 2017: June 17–18, 2017, Austin, Texas

IWLS 2016: June 10–11, 2016, Austin, Texas

IWLS 2015: June 12–13, 2015, Mountain View, California

IWLS 2014: May 30–June 1, 2014, San Francisco, California

IWLS 2013: June 7–8, 2013, Austin, Texas

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IWLS 2002: June 4–7, 2002, New Orleans, Louisiana

IWLS 2001: June 12–15, 2001, Lake Tahoe, California

IWLS 2000: May 31–June 2, 2000, Dana Point, California

ICCAD: International Conference on Computer-Aided Design

DATE: Design, Automation and Test in Europe

ASP-DAC: Asia and South Pacific Design Automation Conference

DAC: Design Automation Conference

ISPD: International Symposium on Physical Design

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