Co-located with the
Design Automation Conference

29th International Workshop
on Logic & Synthesis

July 18 – 19 July 27 – 30, 2020

Moscone Center, San Francisco, CA Virtual Conference

Moscone Center

Our sponsors

IWLS is Moving to a New Home!

We are moving to the new website: https://iwls20.cade.utah.edu/

NEWS: IWLS 2020 A Virtual Experience

Due to the current situation, IWLS is going virtual this year!

Message from the general chair:

Dear IWLS contributors, attendees and enthusiasts,

Due to the current situation, IWLS is also going to embark into the virtual experience. It is the main focus of the organizing committee to provide a way to exchange new ideas and promote logic synthesis in the most engaging way, while accounting for the challenges of having colleagues all over the world. The modalities of the virtual transition will be communicated in due time. IWLS has always been an exemplary workshop for early scientific dissemination and exchange. As such, we would welcome any advices / recommendations that our community might have to make the first virtual IWLS a successful event.

Please feel free to reach out directly to the general chair, Pierre-Emmanuel Gaillardon (pierre-emmanuel.gaillardon@utah.edu) for any ideas.

Best wishes,
Pierre-Emmanuel Gaillardon, on behalf of the IWLS 2020 organizing committee

About IWLS

The International Workshop on Logic and Synthesis (IWLS) is the premier forum for research in synthesis, optimization, and verification of integrated circuits and systems. Research on logic synthesis for emerging technologies and for novel computing platforms, such as nanoscale systems and biological systems, is also strongly encouraged. The workshop encourages early dissemination of ideas and results. The workshop accepts complete papers highlighting important new problems in the early stages of development, without providing complete solutions. The emphasis is on novelty and intellectual rigor.

Topics of interest include, but are not limited to: hardware synthesis and optimization; software synthesis; hardware/software co-synthesis; power and timing analysis; testing, validation and verification; synthesis for reconfigurable architectures; hardware compilation for domain-specific languages; design experiences. Submissions on modeling, analysis, and synthesis for emerging technologies and platforms are particularly encouraged.

The workshop format includes paper presentations, posters, invited talks, social lunch and dinner gatherings, and recreational activities. Accepted papers are distributed exclusively to IWLS participants.

Please download Call for Paper.

Important Dates

It is mandatory to register a paper by submitting an abstract before the deadline below.

Paper abstract submission: April 17, 2020 May 1st, 2020 (extended)
Full paper submission: April 24, 2020 May 8th, 2020 (extended)
Notification of acceptance: June 16, 2020
Final version due: July 3, 2020

Submission Instructions

Only complete papers with original and previously unpublished material are permitted. Submissions must be no longer than 8 pages, double column, 10-point font. Accepted papers are distributed only to IWLS participants.

EasyChair IWLS 2020 submission page

IWLS 2020 Programming Contest: Machine Learning + Logic Synthesis

In 2020, the IWLS organizing committee set up a programming contest. To participate, please follow these steps:

  1. Read the contest description and download the benchmark
  2. Write a computer program to learn an unknown boolean function from a training set consisting of input-output pairs.
  3. Test your solution using the provided validation set. Notice that we will evaluate your function not on the validation set, but on a private test set.
  4. Submit both the program used to generate AIGs given the training data as well as the actual AIG files for each benchmark no later than June 12, 2020 June 26, 2020.

Submission instructions:

  1. Please submit your solution to iwls.contest.2020@gmail.com no later than the contest deadline.
  2. Please feel free to include external links (e.g., Google Drive, GitHub) containing your solution.
  3. Please include the information about the team (participants' names and affiliations) in the submission.
  4. Please include a brief description of your solution.
The submission deadline is extended to June 26, 2020.

Technical Program




Social Activities


Organizing Committee

General Chair Pierre-Emmanuel Gaillardon University of Utah, USA
Program Chairs Luca Amaru / Heinz Riener Synopsys, USA / EPFL, Switzerland
Programming Contest Chair Gai Liu Xilinx Inc, USA
Special Session Chair Tsung-Yi Ho NTHU, Taiwan
Finance Chair Cunxi Yu University of Utah, USA
Proceedings Chair Zhufei Chu Ningbo University, China
Publicity Chair Tsung-Wei Huang University of Utah, USA
Local Chair Vinicius Callegaro Mentor, a Siemens Business, USA

Steering Committee


Technical Program Committee

Luca Amaru    Synopsys, USA
Anna Bernasconi    University of Pisa, Italy
Vinicius Callegaro    Mentor, a Siemens business, USA
Kai-Hui Chang    Avery Design Systems, USA
Mihir Choudhury    IBM T. J. Watson, USA
Zhufei Chu    Ningbo University, China
Sabya Das    Synopsys, USA
Rolf Drechsler    University of Bremen, Germany
Elena Dubrova    KTH, Sweden
Stephen Edwards    Columbia University, USA
Petr Fiser    CTU, Czech Republic
Masahiro Fujita    University of Tokyo, Japan
Pierre-Emmanuel Gaillardon    University of Utah, USA
Tsung-Yi Ho    NTHU, Taiwan
Tsung-Wei Huang    University of Utah, USA
Paolo Ienne    EPFL, Switzerland
Hui-Ru Iris Jiang    National Taiwan University, Taiwan
Jie-Hong Roland Jiang    National Taiwan University, Taiwan
Victor Kravets    IBM T. J. Watson, USA
Gai Liu    Xilinx Inc, USA
Felipe Marranghello    Synopsys, USA
Mayler Martins    Mentor, a Siemens business, USA
Jody Matos    Silvaco, USA
Alan Mishchenko    UC Berkeley, USA
Augusto Neutzling    Cadence, UK
Elie EI Aaraj    Cadence, USA
Vinicius Possani    Synopsys, USA
Madhura Purnaprajna    Amrita University, India
Weikang Qian    Shanghai Jiao Tong University, China
Andre Inacio Reis    UFRGS, Brazil
Heinz Riener    EPFL, Switzerland
Tsutomu Sasao    Meiji University, Japan
Mathias Soeken    Microsoft, USA
Dirk Stroobandt    Ghent University, Belgium
Tiziano Villa    Universita' di Verona, Italy
Robert Wille    Johannes Kepler U., Austria
Cunxi Yu    University of Utah, USA
Zhiru Zhang    Cornell University, USA


The IWLS community maintains a set of logic synthesis benchmarks (IWLS'05 and EPFL), available in various formats.

Mailing List

Subscribe to the IWLS mailing list. (The list is hidden and only its administrator can post to it.)

Links to Past Workshops

IWLS 2019: June 21 - June 23, 2019, EPFL, Lausanne, Switzerland

IWLS 2018: June 23 - June 24, 2018, San Francisco, California

IWLS 2017: June 17 - June 18, 2017, Austin, Texas

IWLS 2016: June 10 - June 11, 2016, Austin, Texas

IWLS 2015: June 12 - June 13, 2015, Mountain View, California

IWLS 2014: May 30 - June 1, 2014, San Francisco, California

IWLS 2013: June 7 - June 8, 2013, Austin, Texas

IWLS 2012: June 1 - June 3, 2012, Berkeley, California

IWLS 2011: June 3 - June 5, 2011, San Diego, California

IWLS 2010: June 18 - June 20, 2010, Irvine, California

IWLS 2009: July 31 - August 2, 2009, Berkeley, California

IWLS 2008: June 4 - 6, 2008, Lake Tahoe, California

IWLS 2007: May 30 - June 1, 2007, San Diego, California

IWLS 2006: June 7 - 9, 2006, Vail, Colorado

IWLS 2005: June 8 - 10, 2005, Lake Arrowhead, California

IWLS 2004: June 2 - 4, 2004, Temecula Creek, California

IWLS 2003: May 28 - 30, 2003, Laguna Beach, California

IWLS 2002: June 4 - 7, 2002, New Orleans, Louisiana

IWLS 2001: June 12 - 15, 2001, Lake Tahoe, California

IWLS 2000: May 31 - June 2, 2000, Dana Point, California

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DAC: Design Automation Conference

ISPD: International Symposium on Physical Design

ISLPED: International Symposium on Low Power Electronics and Design

IWBDA: International Symposium on Bio-Design Automation