2021

30th International Workshop
on Logic & Synthesis

July 19 – 21, 2021

Virtual Conference

Our sponsors

              

The International Workshop on Logic and Synthesis is the premier forum for research in synthesis, optimization, and verification of integrated circuits and systems. Research on logic synthesis for emerging technologies and for novel computing platforms, such as nanoscale systems and biological systems, is also strongly encouraged. The workshop encourages early dissemination of ideas and results. The workshop accepts complete papers highlighting important new problems in the early stages of development, without providing complete solutions. The emphasis is on novelty and intellectual rigor.

Topics of interest include, but are not limited to: hardware synthesis and optimization; software synthesis; hardware/software co-synthesis; power and timing analysis; testing, validation and verification; synthesis for reconfigurable architectures; hardware compilation for domain-specific languages; design experiences. Submissions on modeling, analysis, and synthesis for emerging technologies and platforms are particularly encouraged.

The workshop format includes paper presentations, posters, invited talks, social lunch and dinner gatherings, and recreational activities. Accepted papers are distributed exclusively to IWLS participants.

Check out our call for papers.

Technical Program

TBA

Keynotes

QED and Symbolic QED: Dramatic Advances in Hardware Verification, Debug, and Security
Subhasish Mitra, Stanford, United States

You have all spent weeks or months of onerous manual effort in verifying chips, from writing assertions to running long simulations or debugging hardware failures. We can now detect and localize difficult bugs quickly, in a few seconds or a few hours, during pre-silicon verification and post silicon validation. Quick Error Detection (QED) targets post-silicon validation and debug. Symbolic QED combines QED principles with a formal engine for pre-silicon verification. Extensive industrial studies show that QED and Symbolic QED improve verification productivity dramatically, from several months using existing flows to just a few days, while ensuring high degrees of thoroughness. Beyond bugs, QED principles are also effective in detecting hardware security vulnerabilities. QED techniques have been successfully deployed in industry.

Subhasish Mitra is a Professor of electrical engineering and of computer science from Stanford University, Stanford, CA, USA, where he directs the Stanford Robust Systems Group, coleads the computation focus area of the Stanford SystemX Alliance, and is also a Faculty Member of the Stanford Neurosciences Institute. He holds the Carnot Chair of Excellence in Nanosystems with CEA-LETI, Grenoble, France. His current research interests range broadly across robust computing, nanosystems, very large-scale integration (VLSI) design, validation, test and electronic design automation, and neurosciences. Prof. Mitra was a recipient of the ACM SIGDA/IEEE CEDA A. Richard Newton Technical Impact Award in Electronic Design Automation (a test of time honor), the Semiconductor Research Corporation’s Technical Excellence Award, the Intel Achievement Award (Intels highest corporate honor), and the Presidential Early Career Award for Scientists and Engineers from the White House (the highest United States honor for early-career outstanding scientists and engineers). He and his students published several award winning papers at major venues: ACM/IEEE Design Automation Conference, IEEE International Solid-State Circuits Conference, IEEE International Test Conference, the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE VLSI Test Symposium, and the Symposium on VLSI Technology. He is an ACM Fellow and an IEEE Fellow.

Superconducting accelerators: circuits, design and synthesis
Giovanni De Micheli, EPFL, Switzerland

Superconducting electronics (SCE) provides us with a variety of methods for speeding-up computation, and it suits well the implementation of dataflows. SCE is implemented in various forms and styles, and these imply new and different constraints for logic design. This talk will investigate the relations between circuit styles, design constraints and logic synthesis, in the search for laying a framework for designing SCE in diverse ways and to compare them on significant benchmarks.

Giovanni De Micheli is currently a Professor of electrical engineering and a Professor of computer science with EPF Lausanne, Switzerland. His research interests include several aspects of design technologies for integrated circuits and systems, such as design and synthesis for emerging technologies. He is an ACM Fellow and an IEEE Fellow, a member of the Academia Europaea, and an International Honorary member of the American Academy of Arts and Sciences. He was a recipient of the 2019 ACM/SIGDA Pioneer Award, the 2016 IEEE/CS Harry Goode Award for seminal contributions to design and design tools of Networks on Chips, the 2016 EDAA Lifetime Achievement Award, the 2012 IEEE/CAS Mac Van Valkenburg award for contributions to theory, practice and experimentation in design methods and tools, and the 2003 IEEE Emanuel Piore Award for contributions to computer-aided synthesis of digital systems.

Circuit Learning: A Classical Problem from a Modern Perspective
Jie-Hong Roland Jiang, NTU, Taiwan

Circuit learning is a classical problem in computational learning theory. Representative algorithms for learning different forms of Boolean formulas and learning automata are well known since the 1980s. Recent advancements in logic synthesis, formal verification, and machine learning have revived and reshaped circuit learning methods. In this talk, we will overview the evolving circuit learning algorithms and put them in the context of modern applications.

Jie-Hong R. Jiang received the B.S. and M.S. degrees in Electronics Engineering from National Chiao Tung University, Hsinchu, Taiwan, in 1996 and 1998, respectively, and the Ph.D. degree in Electrical Engineering and Computer Sciences from the University of California, Berkeley, in 2004. He is a Professor of the Department of Electrical Engineering and the Graduate Institute of Electronics Engineering at National Taiwan University. He leads the Applied Logic and Computation Laboratory, and has worked extensively on logic synthesis, formal verification, electronic design automation, and computation models of biological and physical systems. Dr. Jiang is a member of Phi Tau Phi and the Association for Computing Machinery (ACM).



IWLS 2021 Programming Contest

In 2021, the IWLS organizing committee set up a programming contest. To participate, please follow these steps:

  1. Read the contest description.
  2. Write a computer program to learn an unknown multi-output boolean function which performs well on the CIFAR-10 dataset
  3. We consider 3 different size limits: small (where the AIG has no more than 10,000 and-nodes), medium (no more than 100,000 and-nodes), and large (no more than 1,000,000 and-nodes). Each category will have a separate winner.
  4. The score will be based on the Top-1 accuracy on the public CIFAR-10 test set.

Submission instructions:

  1. Please submit your solution to iwls.contest.2021@gmail.com no later than June 11, 2021.
  2. Please submit 3 AIG files in Binary AIGER format named small.aig, medium.aig, and large.aig.
  3. Please also submit your code and a short writeup on the method used. At the top of the write-up, please indicate how many times you peeked at the CIFAR-10 test set in the course of your research.
  4. Please feel free to include external links (e.g., Google Drive, GitHub) containing your solution.
  5. Please include the information about the team (participants' names and affiliations) in the submission.

2nd Logic Synthesis Software School

The 2nd Logic Synthesis Software School (LSSS) will be co-located with IWLS. The LSSS is an informal meeting on software tools for logic synthesis and verification.

The goal of the meeting is to bring together researchers and tool developers in the fields of electronic design automation, logic synthesis, and verification to foster research on open science infrastructure and tools for logic synthesis and verification.

The Logic Synthesis Software School page

Important Dates

It is mandatory to register a paper by submitting an abstract before the deadline below.

Paper abstract submission: April 19, 2021
Full paper submission: April 26, 2021 @ 11.59pm Anywhere on Earth
Notification of acceptance: June 18, 2021
Final version due: June 30, 2021

Submission Instructions

Only complete papers with original and previously unpublished material are permitted. Submissions must be no longer than 8 pages, double column, 10-point font. Accepted papers are distributed only to IWLS participants.

EasyChair IWLS 2021 submission page

Organizing Committee

General Chair Vinicius Callegaro Siemens EDA, USA
Program Committee Chair Cunxi Yu / Gai Liu University of Utah, USA / Xilinx Inc, USA
Program Contest Chair Satrajit Chatterjee / Alan Mishchenko Google, USA / University of California Berkeley, USA
Special Session Chair Luca Amaru Synopsys, USA
Finance Chair Jody Matos Silvaco, USA
Proceedings Chair Zhufei Chu Ningbo University, China
Publicity Chair Eleonora Testa Synopsys, Switzerland
Virtual Chair Augusto Neutzling / Walter Lau Neto Cadence, UK / University of Utah, USA

Steering Committee

Jie-Hong Roland Jiang National Taiwan University, Taiwan
Rolf Drechsler University of Bremen/DFKI GmbH, Germany
Andre Reis UFRGS, Brazil
Dirk Stroobandt Ghent University, Belgium
Alan Mishchenko University of California Berkeley, US

Technical Program Committee (Tentative)

Luca Amaru    Synopsys, USA
Vinicius Callegaro    Siemens EDA, USA
Zhufei Chu    Ningbo University, China
Elie EI Aaraj    Cadence, USA
Petr Fiser    CTU, Czech Republic
Pierre-Emmanuel Gaillardon    University of Utah, USA
Tsung-Yi Ho    NTHU, Taiwan
Tsung-Wei Huang    University of Utah, USA
Jie-Hong Roland Jiang    National Taiwan University, Taiwan
Victor Kravets    IBM T. J. Watson, USA
Walter Lau Neto    University of Utah, USA
Gai Liu    Xilinx Inc, USA
Felipe Marranghello    Synopsys, USA
Jody Matos    Silvaco, USA
Alan Mishchenko    UC Berkeley, USA
Augusto Neutzling    Cadence, UK
Weikang Qian    Shanghai Jiao Tong University, China
Andre Inacio Reis    UFRGS, Brazil
Heinz Riener    EPFL, Switzerland
Tsutomu Sasao    Meiji University, Japan
Mathias Soeken    Microsoft, USA
Eleonora Testa    Synopsys, Switzerland
Tiziano Villa    Universita' di Verona, Italy
Robert Wille    Johannes Kepler U., Austria
Cunxi Yu    University of Utah, USA
Yuan Zhou    Cornell University, USA

Benchmarks

The IWLS community maintains a set of logic synthesis benchmarks (IWLS'05 and EPFL), available in various formats.

Mailing List

Subscribe to the IWLS mailing list. (The list is hidden and only its administrator can post to it.)

Links to Past Workshops

IWLS 2020: July 27 - July 30, 2020, Virtual

IWLS 2019: June 21 - June 23, 2019, San Francisco, California

IWLS 2018: June 23 - June 24, 2018, San Francisco, California

IWLS 2017: June 17 - June 18, 2017, Austin, Texas

IWLS 2016: June 10 - June 11, 2016, Austin, Texas

IWLS 2015: June 12 - June 13, 2015, Mountain View, California

IWLS 2014: May 30 - June 1, 2014, San Francisco, California

IWLS 2013: June 7 - June 8, 2013, Austin, Texas

IWLS 2012: June 1 - June 3, 2012, Berkeley, California

IWLS 2011: June 3 - June 5, 2011, San Diego, California

IWLS 2010: June 18 - June 20, 2010, Irvine, California

IWLS 2009: July 31 - August 2, 2009, Berkeley, California

IWLS 2008: June 4 - 6, 2008, Lake Tahoe, California

IWLS 2007: May 30 - June 1, 2007, San Diego, California

IWLS 2006: June 7 - 9, 2006, Vail, Colorado

IWLS 2005: June 8 - 10, 2005, Lake Arrowhead, California

IWLS 2004: June 2 - 4, 2004, Temecula Creek, California

IWLS 2003: May 28 - 30, 2003, Laguna Beach, California

IWLS 2002: June 4 - 7, 2002, New Orleans, Louisiana

IWLS 2001: June 12 - 15, 2001, Lake Tahoe, California

IWLS 2000: May 31 - June 2, 2000, Dana Point, California

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