31st International Workshop
on Logic & Synthesis

July 18 – 21, 2022

Virtual Conference

Our sponsors


The International Workshop on Logic and Synthesis is the premier forum for research in synthesis, optimization, and verification of integrated circuits and systems. Research on logic synthesis for emerging technologies and for novel computing platforms, such as nanoscale systems and biological systems, is also strongly encouraged. The workshop encourages early dissemination of ideas and results. The workshop accepts complete papers highlighting important new problems in the early stages of development, without providing complete solutions. The emphasis is on novelty and intellectual rigor.

Topics of interest include, but are not limited to: hardware synthesis and optimization; software synthesis; hardware/software co-synthesis; power and timing analysis; testing, validation and verification; synthesis for reconfigurable architectures; hardware compilation for domain-specific languages; design experiences. Submissions on modeling, analysis, and synthesis for emerging technologies and platforms are particularly encouraged.

The workshop format includes paper presentations, posters, invited talks, social gatherings, and recreational activities. Accepted papers are distributed exclusively to IWLS participants.

Check out our call for papers.

Technical Program

The technical program consists of 18 regular talks, 1 short presentation, 3 keynotes and 1 special session.

Best Student Paper Nominations
Paper #10: An Automated Testing and Debugging Toolkit for Gate-Level Logic Synthesis Applications
(Best Student Paper Award)
Siang-Yun Lee (EPFL, Switzerland), Heinz Riener (Cadence Design Systems, Germany) and Giovanni De Micheli (EPFL, Switzerland)
Paper #15: Language Equation Solving via Boolean Automata Manipulation
Wan-Hsuan Lin (National Taiwan University, Taiwan), Chia-Hsuan Su (National Taiwan University, Taiwan) and Jie-Hong Roland Jiang (National Taiwan University, Taiwan)
Paper #16: Partial Equivalence Checking of Quantum Circuits
Tian-Fu Chen (National Taiwan University, Taiwan), Jie-Hong Roland Jiang (National Taiwan University, Taiwan) and Min-Hsiu Hsieh (National Taiwan University, Taiwan)
Paper #26: Quantifier Elimination in Stochastic Boolean Satisfiability
Hao-Ren Wang (National Taiwan University, Taiwan), Kuan-Hua Tu (National Taiwan University, Taiwan), Jie-Hong Roland Jiang (National Taiwan University, Taiwan) and Christoph Scholl (University of Freiburg, Germany)

Best Presentation Award
Polynomial Formal Verification of Approximate Adders
Martha Schnieber (University of Bremen, Germany), Saman Froehlich (University of Bremen, Germany) and Rolf Drechsler (University of Bremen, Germany)
Talk @Youtube

Programming Contest - Top-3 Teams
1st team: EPFL (École polytechnique fédérale de Lausanne)
Andrea Costamagna, Siang-Yun Lee, Alessandro Tempia Calvino, Hanyu Wang, Mingfei Yu, Professor Giovanni de Micheli
Talk @Youtube
2nd team: Team UCB (University of California, Berkeley)
Yukio Miyasaka
Talk @Youtube
3rd team: team TUW (Technische Universität Wien)
Franz Reichl, Friedrich Slivovsky, Stefan Szeider
Talk @Youtube


Agile Spatial Hardware Specialization
Yun (Eric) Liang, Peking University, China

Tensor algebra finds applications in various domains, and these applications, especially when accelerated on spatial hardware accelerators, can deliver high performance and low power. Spatial hardware accelerator exhibits complex design space. Prior approaches based on manual implementation lead to low programming productivity, rendering thorough design space exploration impossible. We propose a series of works that can formally represent the hardware dataflow and generate the hardware automatically.

Yun (Eric) Liang is currently an associate professor (with tenure) in the school of EECS, Peking University, China. His research interest is at the hardware-software interface with work spanning electronic design automation (EDA), computer architecture, and embedded system design. He has authored over 100 scientific publications in the premier international journals and conferences in this domain. His research has been recognized by best paper awards at FCCM 2011 and ICCAD 2017 and best paper nominations at PPoPP 2019, DAC 2017, ASPDAC 2016, DAC 2012, FPT 2011, CODES+ISSS 2008. Prof Liang serves as Associate Editor for ACM Transactions in Embedded Computing Systems (TECS) and ACM Transactions on Reconfigurable Technology and Systems (TRETS) and serves in the program committees in the premier conferences in the related domain including (MICRO, HPCA, DAC, FPGA, FCCM, etc).

High-Level Synthesis of Dynamically Scheduled Circuits
Lana Josipović, ETH Zurich, Switzerland

High-level synthesis (HLS) tools generate digital hardware designs from high-level programming languages (e.g., C/C++) and promise to liberate designers from low-level hardware description details. Yet, HLS tools are still acceptable only for certain classes of applications and are criticized for the difficulty of extracting the desired level of performance: generating good circuits still requires tedious code restructuring and hardware design expertise. In this talk, I will present a new HLS methodology that produces dynamically scheduled, dataflow circuits out of C/C++ code; the resulting circuits achieve good performance out-of-the-box and realize behaviors that are beyond the capabilities of standard HLS tools. I will outline mathematical models to optimize the performance and area of the resulting circuits, as well as techniques to achieve characteristics that standard HLS cannot support, such as out-of-order memory accesses and speculative execution. These contributions redefine the HLS paradigm by introducing characteristics of modern superscalar processors to hardware designs; such behaviors are key for specialized computing to be successful in new contexts and broader application domains.

Lana Josipović is an Assistant Professor in the Department of Information Technology and Electrical Engineering at ETH Zurich. Prior to joining ETH Zurich in January 2022, she received a Ph.D. degree in Computer Science from EPFL, Switzerland. Her research interests include reconfigurable computing and electronic design automation, with an emphasis on high-level synthesis techniques to generate hardware designs from high-level programming languages. She developed Dynamatic, an open-source high-level synthesis tool that produces dynamically scheduled circuits from C/C++ code. She is a recipient of the EDAA Outstanding Dissertation Award, Google Ph.D. Fellowship in Systems and Networking, Google Women Techmakers Scholarship, and Best Paper Award at FPGA'20.

Practice on Performance Autotuning in AI Compute Chip
Peipei Zhou, University of Pittsburgh, USA

Modern AI compute SOCs have abundant computation cores, interconnects & high-bandwidth memory (HBM) resources. When facing enormous different neural network architectures, how to program AI compute chips to make full use of the system resources becomes challenging. In this talk, I will share an automated code generation framework "Autotuning through design space pruning & schedule templates" to program a commercial AI compute chip to achieve improvements in both accelerator performance and coding efficiency.

Peipei Zhou joined the University of Pittsburgh, ECE department as a Tenure-Track Assistant Professor starting September 2021. She obtained my Ph.D. in Computer Science from University of California, Los Angeles in 2019 supervised by Prof. Jason Cong, who leads UCLA VAST(VLSI Architecture, Synthesis and Technology) Group and CDSC (The Center for Domain-Specific Computing). Her major interest is in Customized Computer Architecture and Programming Abstraction for Applications including Healthcare, e.g., Precision Medicine and Artificial Intelligence. She has received “Outstanding Recognition in Research” from UCLA Samueli School of Engineering in 2019, 2019 TCAD Donald O. Pederson Best Paper Award, 2018 ICCAD Best Paper Nominee, and 2018 ISPASS Best Paper Nominee.


Instructions available!

The workshop will be held on Zoom and has no formal registration.

Please send an email to iwls2022.join@gmail.com to receive your meeting invitations.

IWLS 2022 Programming Contest

Contest submission closed.

The goal of this year's contest is to synthesize small circuits for completely-specified multi-output Boolean functions represented using truth tables. Participants should find competitive solutions for different benchmarks using a variety of novel break-through methods (e.g., search and enumeration, new decomposition, etc.).

To participate, check out the contest description and download the benchmark.

Please submit your solution sending an email to iwls2022.contest@gmail.com no later than June 20, 2022 July 4, 2022 July 11, 2022.

Contest award:

  • 1st Place Award: $1,000 USD
  • 2nd Place Award: $750 USD
  • 3rd Place Award: $500 USD

Important Dates

Paper submission closed.

Paper abstract submission: April 11, 2022 April 25, 2022
Full paper submission: April 18, 2022 May 2, 2022 @ 11.59pm Anywhere on Earth
Notification of acceptance: June 24, 2022
Final version due: July 06, 2022

Submission Instructions

Only complete papers with original and previously unpublished material are permitted. Submissions must be no longer than 8 pages, double column, 10-point font. Accepted papers are distributed only to IWLS participants.


  • Best Student Paper Award: $1,000 USD
  • Best Presentation Award: $1,000 USD

EasyChair IWLS 2022 submission page

Organizing Committee

General Chair Luca Amaru Synopsys, USA
Program Committee Chairs Eleonora Testa / Valentina Ciriani Synopsys, USA / University of Milan, IT
Program Contest Chairs Alan Mishchenko / Satrajit Chatterjee University of California Berkeley, USA / Google, USA
Special Session Chair Cunxi Yu Univerisy of Utah, USA
Finance Chair Zhufei Chu Ningbo University, China
Proceedings Chair Walter Lau Neto Univerisy of Utah, USA
Publicity Chair Augusto Neutzling Cadence, UK
Virtual Chair Giulia Meuli Synopsys, IT

Technical Program Committee

Luca Amaru    Synopsys, USA
Anna Bernasconi    Università di Pisa, Italy
Vinicius Callegaro    Siemens EDA, USA
Sat Chatterjee    Google, USA
Zhufei Chu    Ningbo University, China
Valentina Ciriani    Università degli Studi di Milano, Italy
Stephan Eggersglüß    Siemens EDA, Germany
Petr Fišer    CTU, Czech Republic
Jie-Hong Roland Jiang    National Taiwan University, Taiwan
Victor Kravets    IBM, USA
Walter Lau Neto    University of Utah, USA
Giulia Meuli    Synopsys, Italy
Alan Mishchenko    UC Berkeley, USA
Augusto Neutzling    Cadence Design System, UK
Weikang Qian    Shanghai Jiao Tong University, China
Andre Reis    UFRGS, Brazil
Heinz Riener    Cadence Design System, Germany
Tsutomu Sasao    Meiji University, Japan
Mathias Soeken    Microsoft, USA
Eleonora Testa    Synopsys, USA
Tiziano Villa    Università degli Studi di Verona, Italy
Robert Wille    Johannes Kepler University, Austria
Cunxi Yu    University of Utah, USA


The IWLS community maintains a set of logic synthesis benchmarks (IWLS'05 and EPFL), available in various formats.

Mailing List

Subscribe to the IWLS mailing list. (The list is hidden and only its administrator can post to it.)

Links to Past Workshops

IWLS 2021: July 19 - July 22, 2021, Virtual

IWLS 2020: July 27 - July 30, 2020, Virtual

IWLS 2019: June 21 - June 23, 2019, San Francisco, California

IWLS 2018: June 23 - June 24, 2018, San Francisco, California

IWLS 2017: June 17 - June 18, 2017, Austin, Texas

IWLS 2016: June 10 - June 11, 2016, Austin, Texas

IWLS 2015: June 12 - June 13, 2015, Mountain View, California

IWLS 2014: May 30 - June 1, 2014, San Francisco, California

IWLS 2013: June 7 - June 8, 2013, Austin, Texas

IWLS 2012: June 1 - June 3, 2012, Berkeley, California

IWLS 2011: June 3 - June 5, 2011, San Diego, California

IWLS 2010: June 18 - June 20, 2010, Irvine, California

IWLS 2009: July 31 - August 2, 2009, Berkeley, California

IWLS 2008: June 4 - 6, 2008, Lake Tahoe, California

IWLS 2007: May 30 - June 1, 2007, San Diego, California

IWLS 2006: June 7 - 9, 2006, Vail, Colorado

IWLS 2005: June 8 - 10, 2005, Lake Arrowhead, California

IWLS 2004: June 2 - 4, 2004, Temecula Creek, California

IWLS 2003: May 28 - 30, 2003, Laguna Beach, California

IWLS 2002: June 4 - 7, 2002, New Orleans, Louisiana

IWLS 2001: June 12 - 15, 2001, Lake Tahoe, California

IWLS 2000: May 31 - June 2, 2000, Dana Point, California

Related Conferences

ICCAD: International Conference on Computer-Aided Design

DATE: Design, Automation and Test in Europe

ASPDAC: Asia and South Pacific Design Automation Conference

DAC: Design Automation Conference

ISPD: International Symposium on Physical Design

ISLPED: International Symposium on Low Power Electronics and Design

IWBDA: International Symposium on Bio-Design Automation