Co-located with the
Design Automation Conference

23rd International Workshop
on Logic & Synthesis

May 30 – June 1, 2014

Galleria Park Hotel — San Francisco, CA
Galleria Park Hotel

Our sponsors


The International Workshop on Logic and Synthesis is the premier forum for research in synthesis, optimization, and verification of integrated circuits and systems. Research on logic synthesis for emerging technologies and for novel computing platforms, such as nanoscale systems and biological systems, is also strongly encouraged. The workshop encourages early dissemination of ideas and results. The workshop accepts complete papers highlighting important new problems in the early stages of development, without providing complete solutions. The emphasis is on novelty and intellectual rigor.

Call for Papers

Call for Papers in PDF

Topics of interest include, but are not limited to: hardware synthesis and optimization; software synthesis; hardware/software co-synthesis; power and timing analysis; testing, validation and verification; synthesis for reconfigurable architectures; hardware compilation for domain-specific languages; design experiences. Submissions on modeling, analysis and synthesis for emerging technologies and platforms are particularly encouraged.

The workshop format includes paper presentations, posters, invited talks, social lunch and dinner gatherings, and recreational activities. Accepted papers are distributed exclusively to IWLS participants.

Technical Program

The technical program consists of 19 regular talks, 2 keynotes and 1 special session. A social event is currently planned for Saturday May 31 evening.


SAT Modulo Monotonic Theories
Alan J. Hu, University of British Columbia

I will present the concept of a "monotonic theory" and show how to build efficient SMT (SAT Modulo Theory) solvers, including efficient theory propagation and clause learning, for such theories. Examples of monotonic theories include graph properties such as reachability, shortest path, connected components, minimum spanning tree, and max-flow/min-cut, and we demonstrate our framework by building SMT solvers for each of these theories. We apply these solvers to procedural content generation problems, demonstrating major speed-ups over state-of-the-art approaches based on SAT or Answer Set Programming, and easily solving several instances that were previously impractical to solve. I believe this approach also holds promise for physical-design-aware synthesis (although we don't have experimental results for that yet). [This is joint work with Sam Bayless, Noah Bayless, and Holger Hoos.]

Alan J. Hu received his B.S. (Honors, with Academic Distinction) and PhD degrees from Stanford University. He is a Professor and former Associate Head in the Computer Science Department at the University of British Columbia. For over 20 years, his main research focus has been automated, practical techniques for formal verification. He has served on the program committees of all major CAD and formal verification conferences, and chaired or co-chaired CAV (1998), HLDVT (2003), FMCAD (2004), HVC (2008), and ICCAD (2011). He was also a Technical Working Group Key Contributor on the 2001 International Technology Roadmap for Semiconductors, and is a member of the Technical Advisory Board of Jasper Design Automation.

Visual Cortex on Silicon
Vijaykrishnan Narayanan, Penn State

There has been a rapid growth in use of cameras for a wide variety of applications. However, these cameras lack any significant cognitive abilities and are still predominantly used as recording devices. Recent advances in our understanding of the human visual cortex as well as the emergence of new implementation technologies provides a unique opportunity of realizing smart cognitive cameras. This talk will provide design experiences and challenges in designing such cognitive systems using reconfigurable fabrics and emerging devices.

Vijaykrishnan Narayanan is a Professor of Computer Science and Engineering and Electrical Engineering at The Pennsylvania State University. His research and teaching interests include embedded systems, computer architecture, system design using emerging device technologies and power-aware computing. He has deep interests in cross-disciplinary advances and has led and participated in such projects. He is the Editor-in-Chief of IEEE TCAD and served as the Editor-in-Chief for ACM Journal of Emerging Technologies in Computing Systems. He has won several awards including the 2012 ASPDAC Ten-year retrospective Most influential paper, 2012 Penn State Alumni Society Premier Research Award and 2010 Outstanding Alumnus Award from SVCE, India. He is a fellow of IEEE.

Special Session on Hardware Security

Strong Physical Unclonable Functions: A Tale of Attacks and Countermeasures
Farinaz Koushanfar, Rice University

Over the last decade, a set of new security and protection mechanisms, tools, protocols, and devices based on physical unclonability and disorder has emerged. Harnessing the inherent, indelible, and unclonable mesoscopic disorders of the physical processes and phenomena, could lead to several advantages which include: providing an alternative form of digital storage which is also inerasable and unforgeable; creating unique signatures; and enabling a novel security foundation. In this talk, I discuss our ongoing efforts in establishing the applicability and robustness of an important class of physical disorder-based security known as strong physical unclonable function. I emphasize on the establishment of security assumptions, properties, and protocols as well as our evolving understanding of sophisticated attacks and countermeasures.

Farinaz Koushanfar is an Associate Professor with the Department of Electrical and Computer Engineering, Rice University, where she directs the Adaptive Computing and Embedded Systems (ACES) Lab. Her research interests include adaptive and low power embedded systems design, hardware security, and design intellectual property protection.

Building Secure Reliable Hardware Roots-of-Trust: Are PUFs Enough?
Ken Mai, Carnegie Mellon University

Hardware roots-of-trust are often regarded as the bedrock upon which the rest of the system securities lies. They perform basic security critical functions such as cryptographic key storage/generation, device and software authentication, secure data storage, and data encryption/hashing. Further, these blocks must be resistant to various forms of non-invasive and invasive attacks and tampering. We will examine the necessary features and characteristics of hardware roots-of-trust and if current technologies can meet those needs. Specifically, we will focus on the design and implementation of physical unclonable functions (PUFs) and secure logic families. Finally, we will suggest lines of research to improve PUFs and secure logic for future secure systems.

Ken Mai received his B.S., M.S., and Ph.D. degrees in electrical engineering from Stanford University. He joined the Electrical and Computer Engineering faculty of Carnegie Mellon University in 2005. His primary research interests are in VLSI design and integrated circuit security, specifically physical unclonable functions (PUFs), efficient cryptographic accelerator implementations, side-channel attack countermeasures, and anti-counterfeiting. He was the recipient of an NSF CAREER award in 2007, the George Tallman Ladd Research Award in 2008, and the Eta Kappa Nu Excellence in Teaching award in 2014.


    Until May 6   From May 7
ACM/IEEE members:   Students   $200   $300
  Others   $300   $400
Non ACM/IEEE members:   Students   $250   $350
  Others   $400   $500

The cost of registration includes breakfasts, lunches, social event and coffee break service.

Register for IWLS on the DAC registration page following the instructions below:

  1. Go to https://reg.mpassociates.com/reglive/PromoCode.aspx?confid=170 and click on "Register". This will direct you to the registration page.
  2. Complete all the contact information and enter your membership status. Click "Select Your Participation". This will bring you to the product choice page.
  3. Open the "Colocated Conferences" tab, select the IWLS option, and click on "Checkout" to proceed to checkout.
For any question regarding the registration process, please email Register@dac.com or call the DAC offices at +1-303-530-4333.


The conference venue is the Galleria Park Hotel, 191 Sutter Street, San Francisco, CA 94104. The IWLS conference rate for sleeping rooms at the Galleria Park Hotel is $179 per night and this rate is available for attendees from May 29, 2014 until June 6, 2014. The cut-off date for room reservations is May 1, 2014. Check-in time is 3 pm, check-out time is 12 pm.

Attendees can book their reservations on http://www.galleriapark.com and, when making their reservations, they can enter the Group Code 1405ACM~_001 to get the discounted rates. Otherwise, guests can reach the hotel reservations team at +1-800-792-9639 and reference the ACM~IWLS2014 block.

Status (30th April): Please note that the hotel reports plenty of rooms for the period between May 29 and June 1 but a very reduced room availability afterwards. The hotel suggests to contact them by phone or e-mail if it is not possibile to book the entire week on the online system.

Important Dates

Abstract submission: February 28, 2014
Submission deadline for papers: March 7, 2014 @ 11.59pm Anywhere on Earth
Acceptance notification: April 4, 2014
Final version due April 25, 2014

It is mandatory to register a paper by submitting an abstract before the deadline below.
The submission deadline is final. There will be no extension.

Submission instructions

Only complete papers with original and previously unpublished material are permitted. Submissions must be no longer than 8 pages, double column, 10-point font. Accepted papers are distributed only to IWLS participants.

EasyChair IWLS 2014 submission page

Organizing Committee

General Chair Dirk Stroobandt Ghent University, Belgium
Program Chair Paolo Ienne EPFL, Switzerland
Special Sessions Chair Shobha Vasudevan University of Illinois Urbana-Champaign, US

Steering Committee

Ilya Wagner Intel, US
Valeria Bertacco University of Michigan, US
Philip Brisk University of California Riverside, US
Stephen A. Edwards Columbia University, US
Alan Mishchenko University of California Berkeley, US

Technical Program Committee

J. Anderson University of Toronto, Canada V. Bertacco University of Michigan, US
P. Brisk University of California Riverside, US K.-H. Chang Avery Design Systems, US
E. Dubrova KTH, Sweden S. A. Edwards Columbia University, US
N. Jayakumar Juniper Networks, US H.-R. Jiang National Chiao Tung University, ROC
J.-H. Jiang National Taiwan University, ROC T. Kam Intel, US
V. Kravets IBM T. J. Watson, US S. Krishnaswamy Columbia University, US
A. Mishchenko U. of California Berkeley, US N. Miskov-Zivanov CMU, US
M. Moffitt IBM Research, US R. Murgai Synopsys, US
D. Novo EPFL, Switzerland S. Nowick Columbia University, US
H. Parandeh Afshar Qualcomm, US A. Pellegrini University of Michigan, US
M. Purnaprajna Indian Institute of Science, India W. Qian U. of Michigan-Shanghai Jiao-Tong, PRC
M. Riedel University of Minnesota, US K. Rupnow NTU and ADSC, Singapore
T. Shiple Synopsys, US C. Stangier Synopsys, Germany
D. Stroobandt Ghent University, Belgium C. Sze IBM Research, US
T. Villa Università di Verona, Italy I. Wagner Intel, US
C.-Y. Wang National Tsing Hua University, ROC T. Welp University of California Berkeley, US


The IWLS community maintains a set of benchmarks, synthesized and mapped in Verilog and OpenAccess.

Links to Past Workshops

IWLS 2013: June 7 - June 8, 2013, Austin, Texas

IWLS 2012: June 1 - June 3, 2012, Berkeley, California

IWLS 2011: June 3 - June 5, 2011, San Diego, California

IWLS 2010: June 18 - June 20, 2010, Irvine, California

IWLS 2009: July 31 - August 2, 2009, Berkeley, California

IWLS 2008: June 4 - 6, 2008, Lake Tahoe, California

IWLS 2007: May 30 - June 1, 2007, San Diego, California

IWLS 2006: June 7 - 9, 2006, Vail, Colorado

IWLS 2005: June 8 - 10, 2005, Lake Arrowhead, California

IWLS 2004: June 2 - 4, 2004, Temecula Creek, California

IWLS 2003: May 28 - 30, 2003, Laguna Beach, California

IWLS 2002: June 4 - 7, 2002, New Orleans, Louisiana

IWLS 2001: June 12 - 15, 2001, Lake Tahoe, California

IWLS 2000: May 31 - June 2, 2000, Dana Point, California

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